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de5bbad677
Some BUG_ON checks can be detected at compile time rather than at runtime. Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
330 lines
9.6 KiB
C
330 lines
9.6 KiB
C
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#include <linux/cache.h>
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#include <linux/delay.h>
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#include <linux/uaccess.h>
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <asm/atomic.h>
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#include <asm/futex.h>
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#include <arch/chip.h>
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/* See <asm/atomic_32.h> */
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#if ATOMIC_LOCKS_FOUND_VIA_TABLE()
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/*
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* A block of memory containing locks for atomic ops. Each instance of this
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* struct will be homed on a different CPU.
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*/
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struct atomic_locks_on_cpu {
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int lock[ATOMIC_HASH_L2_SIZE];
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} __attribute__((aligned(ATOMIC_HASH_L2_SIZE * 4)));
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static DEFINE_PER_CPU(struct atomic_locks_on_cpu, atomic_lock_pool);
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/* The locks we'll use until __init_atomic_per_cpu is called. */
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static struct atomic_locks_on_cpu __initdata initial_atomic_locks;
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/* Hash into this vector to get a pointer to lock for the given atomic. */
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struct atomic_locks_on_cpu *atomic_lock_ptr[ATOMIC_HASH_L1_SIZE]
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__write_once = {
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[0 ... ATOMIC_HASH_L1_SIZE-1] (&initial_atomic_locks)
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};
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#else /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */
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/* This page is remapped on startup to be hash-for-home. */
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int atomic_locks[PAGE_SIZE / sizeof(int) /* Only ATOMIC_HASH_SIZE is used */]
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__attribute__((aligned(PAGE_SIZE), section(".bss.page_aligned")));
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#endif /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */
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static inline int *__atomic_hashed_lock(volatile void *v)
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{
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/* NOTE: this code must match "sys_cmpxchg" in kernel/intvec.S */
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#if ATOMIC_LOCKS_FOUND_VIA_TABLE()
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unsigned long i =
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(unsigned long) v & ((PAGE_SIZE-1) & -sizeof(long long));
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unsigned long n = __insn_crc32_32(0, i);
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/* Grab high bits for L1 index. */
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unsigned long l1_index = n >> ((sizeof(n) * 8) - ATOMIC_HASH_L1_SHIFT);
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/* Grab low bits for L2 index. */
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unsigned long l2_index = n & (ATOMIC_HASH_L2_SIZE - 1);
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return &atomic_lock_ptr[l1_index]->lock[l2_index];
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#else
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/*
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* Use bits [3, 3 + ATOMIC_HASH_SHIFT) as the lock index.
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* Using mm works here because atomic_locks is page aligned.
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*/
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unsigned long ptr = __insn_mm((unsigned long)v >> 1,
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(unsigned long)atomic_locks,
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2, (ATOMIC_HASH_SHIFT + 2) - 1);
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return (int *)ptr;
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#endif
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}
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#ifdef CONFIG_SMP
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/* Return whether the passed pointer is a valid atomic lock pointer. */
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static int is_atomic_lock(int *p)
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{
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#if ATOMIC_LOCKS_FOUND_VIA_TABLE()
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int i;
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for (i = 0; i < ATOMIC_HASH_L1_SIZE; ++i) {
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if (p >= &atomic_lock_ptr[i]->lock[0] &&
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p < &atomic_lock_ptr[i]->lock[ATOMIC_HASH_L2_SIZE]) {
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return 1;
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}
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}
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return 0;
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#else
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return p >= &atomic_locks[0] && p < &atomic_locks[ATOMIC_HASH_SIZE];
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#endif
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}
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void __atomic_fault_unlock(int *irqlock_word)
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{
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BUG_ON(!is_atomic_lock(irqlock_word));
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BUG_ON(*irqlock_word != 1);
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*irqlock_word = 0;
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}
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#endif /* CONFIG_SMP */
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static inline int *__atomic_setup(volatile void *v)
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{
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/* Issue a load to the target to bring it into cache. */
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*(volatile int *)v;
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return __atomic_hashed_lock(v);
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}
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int _atomic_xchg(atomic_t *v, int n)
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{
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return __atomic_xchg(&v->counter, __atomic_setup(v), n).val;
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}
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EXPORT_SYMBOL(_atomic_xchg);
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int _atomic_xchg_add(atomic_t *v, int i)
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{
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return __atomic_xchg_add(&v->counter, __atomic_setup(v), i).val;
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}
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EXPORT_SYMBOL(_atomic_xchg_add);
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int _atomic_xchg_add_unless(atomic_t *v, int a, int u)
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{
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/*
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* Note: argument order is switched here since it is easier
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* to use the first argument consistently as the "old value"
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* in the assembly, as is done for _atomic_cmpxchg().
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*/
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return __atomic_xchg_add_unless(&v->counter, __atomic_setup(v), u, a)
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.val;
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}
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EXPORT_SYMBOL(_atomic_xchg_add_unless);
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int _atomic_cmpxchg(atomic_t *v, int o, int n)
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{
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return __atomic_cmpxchg(&v->counter, __atomic_setup(v), o, n).val;
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}
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EXPORT_SYMBOL(_atomic_cmpxchg);
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unsigned long _atomic_or(volatile unsigned long *p, unsigned long mask)
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{
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return __atomic_or((int *)p, __atomic_setup(p), mask).val;
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}
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EXPORT_SYMBOL(_atomic_or);
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unsigned long _atomic_andn(volatile unsigned long *p, unsigned long mask)
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{
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return __atomic_andn((int *)p, __atomic_setup(p), mask).val;
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}
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EXPORT_SYMBOL(_atomic_andn);
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unsigned long _atomic_xor(volatile unsigned long *p, unsigned long mask)
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{
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return __atomic_xor((int *)p, __atomic_setup(p), mask).val;
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}
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EXPORT_SYMBOL(_atomic_xor);
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u64 _atomic64_xchg(atomic64_t *v, u64 n)
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{
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return __atomic64_xchg(&v->counter, __atomic_setup(v), n);
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}
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EXPORT_SYMBOL(_atomic64_xchg);
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u64 _atomic64_xchg_add(atomic64_t *v, u64 i)
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{
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return __atomic64_xchg_add(&v->counter, __atomic_setup(v), i);
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}
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EXPORT_SYMBOL(_atomic64_xchg_add);
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u64 _atomic64_xchg_add_unless(atomic64_t *v, u64 a, u64 u)
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{
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/*
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* Note: argument order is switched here since it is easier
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* to use the first argument consistently as the "old value"
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* in the assembly, as is done for _atomic_cmpxchg().
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*/
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return __atomic64_xchg_add_unless(&v->counter, __atomic_setup(v),
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u, a);
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}
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EXPORT_SYMBOL(_atomic64_xchg_add_unless);
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u64 _atomic64_cmpxchg(atomic64_t *v, u64 o, u64 n)
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{
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return __atomic64_cmpxchg(&v->counter, __atomic_setup(v), o, n);
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}
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EXPORT_SYMBOL(_atomic64_cmpxchg);
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static inline int *__futex_setup(int __user *v)
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{
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/*
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* Issue a prefetch to the counter to bring it into cache.
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* As for __atomic_setup, but we can't do a read into the L1
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* since it might fault; instead we do a prefetch into the L2.
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*/
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__insn_prefetch(v);
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return __atomic_hashed_lock((int __force *)v);
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}
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struct __get_user futex_set(int __user *v, int i)
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{
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return __atomic_xchg((int __force *)v, __futex_setup(v), i);
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}
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struct __get_user futex_add(int __user *v, int n)
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{
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return __atomic_xchg_add((int __force *)v, __futex_setup(v), n);
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}
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struct __get_user futex_or(int __user *v, int n)
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{
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return __atomic_or((int __force *)v, __futex_setup(v), n);
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}
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struct __get_user futex_andn(int __user *v, int n)
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{
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return __atomic_andn((int __force *)v, __futex_setup(v), n);
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}
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struct __get_user futex_xor(int __user *v, int n)
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{
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return __atomic_xor((int __force *)v, __futex_setup(v), n);
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}
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struct __get_user futex_cmpxchg(int __user *v, int o, int n)
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{
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return __atomic_cmpxchg((int __force *)v, __futex_setup(v), o, n);
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}
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/*
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* If any of the atomic or futex routines hit a bad address (not in
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* the page tables at kernel PL) this routine is called. The futex
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* routines are never used on kernel space, and the normal atomics and
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* bitops are never used on user space. So a fault on kernel space
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* must be fatal, but a fault on userspace is a futex fault and we
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* need to return -EFAULT. Note that the context this routine is
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* invoked in is the context of the "_atomic_xxx()" routines called
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* by the functions in this file.
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*/
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struct __get_user __atomic_bad_address(int __user *addr)
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{
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if (unlikely(!access_ok(VERIFY_WRITE, addr, sizeof(int))))
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panic("Bad address used for kernel atomic op: %p\n", addr);
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return (struct __get_user) { .err = -EFAULT };
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}
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#if CHIP_HAS_CBOX_HOME_MAP()
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static int __init noatomichash(char *str)
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{
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pr_warning("noatomichash is deprecated.\n");
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return 1;
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}
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__setup("noatomichash", noatomichash);
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#endif
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void __init __init_atomic_per_cpu(void)
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{
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#if ATOMIC_LOCKS_FOUND_VIA_TABLE()
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unsigned int i;
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int actual_cpu;
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/*
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* Before this is called from setup, we just have one lock for
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* all atomic objects/operations. Here we replace the
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* elements of atomic_lock_ptr so that they point at per_cpu
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* integers. This seemingly over-complex approach stems from
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* the fact that DEFINE_PER_CPU defines an entry for each cpu
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* in the grid, not each cpu from 0..ATOMIC_HASH_SIZE-1. But
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* for efficient hashing of atomics to their locks we want a
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* compile time constant power of 2 for the size of this
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* table, so we use ATOMIC_HASH_SIZE.
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*
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* Here we populate atomic_lock_ptr from the per cpu
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* atomic_lock_pool, interspersing by actual cpu so that
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* subsequent elements are homed on consecutive cpus.
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*/
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actual_cpu = cpumask_first(cpu_possible_mask);
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for (i = 0; i < ATOMIC_HASH_L1_SIZE; ++i) {
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/*
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* Preincrement to slightly bias against using cpu 0,
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* which has plenty of stuff homed on it already.
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*/
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actual_cpu = cpumask_next(actual_cpu, cpu_possible_mask);
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if (actual_cpu >= nr_cpu_ids)
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actual_cpu = cpumask_first(cpu_possible_mask);
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atomic_lock_ptr[i] = &per_cpu(atomic_lock_pool, actual_cpu);
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}
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#else /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */
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/* Validate power-of-two and "bigger than cpus" assumption */
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BUILD_BUG_ON(ATOMIC_HASH_SIZE & (ATOMIC_HASH_SIZE-1));
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BUG_ON(ATOMIC_HASH_SIZE < nr_cpu_ids);
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/*
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* On TILEPro we prefer to use a single hash-for-home
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* page, since this means atomic operations are less
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* likely to encounter a TLB fault and thus should
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* in general perform faster. You may wish to disable
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* this in situations where few hash-for-home tiles
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* are configured.
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*/
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BUG_ON((unsigned long)atomic_locks % PAGE_SIZE != 0);
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/* The locks must all fit on one page. */
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BUILD_BUG_ON(ATOMIC_HASH_SIZE * sizeof(int) > PAGE_SIZE);
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/*
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* We use the page offset of the atomic value's address as
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* an index into atomic_locks, excluding the low 3 bits.
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* That should not produce more indices than ATOMIC_HASH_SIZE.
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*/
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BUILD_BUG_ON((PAGE_SIZE >> 3) > ATOMIC_HASH_SIZE);
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#endif /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */
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/* The futex code makes this assumption, so we validate it here. */
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BUILD_BUG_ON(sizeof(atomic_t) != sizeof(int));
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}
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