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9287d95ea1
This patch is for supporting a new target platform, Renesas M32104UT evaluation board. The M32104UT is an eval board based on an uT-Engine specification. This board has an MMU-less M32R family processor, M32104. http://www-wa0.personal-media.co.jp/pmc/archive/te/te_m32104_e.pdf This board is one of the most popular M32R platform, so we have ported Linux/M32R to it. Signed-off-by: Naoto Sugai <Sugai.Naoto@ak.MitsubishiElectric.co.jp> Signed-off-by: Hirokazu Takata <takata@linux-m32r.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
68 lines
2.9 KiB
C
68 lines
2.9 KiB
C
#ifndef _ASM_M32R_CACHEFLUSH_H
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#define _ASM_M32R_CACHEFLUSH_H
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#include <linux/config.h>
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#include <linux/mm.h>
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extern void _flush_cache_all(void);
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extern void _flush_cache_copyback_all(void);
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#if defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104)
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#define flush_cache_all() do { } while (0)
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#define flush_cache_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) do { } while (0)
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#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
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#define flush_dcache_page(page) do { } while (0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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#ifndef CONFIG_SMP
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#define flush_icache_range(start, end) _flush_cache_copyback_all()
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#define flush_icache_page(vma,pg) _flush_cache_copyback_all()
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#define flush_icache_user_range(vma,pg,adr,len) _flush_cache_copyback_all()
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#define flush_cache_sigtramp(addr) _flush_cache_copyback_all()
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#else /* CONFIG_SMP */
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extern void smp_flush_cache_all(void);
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#define flush_icache_range(start, end) smp_flush_cache_all()
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#define flush_icache_page(vma,pg) smp_flush_cache_all()
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#define flush_icache_user_range(vma,pg,adr,len) smp_flush_cache_all()
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#define flush_cache_sigtramp(addr) _flush_cache_copyback_all()
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#endif /* CONFIG_SMP */
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#elif defined(CONFIG_CHIP_M32102)
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#define flush_cache_all() do { } while (0)
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#define flush_cache_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) do { } while (0)
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#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
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#define flush_dcache_page(page) do { } while (0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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#define flush_icache_range(start, end) _flush_cache_all()
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#define flush_icache_page(vma,pg) _flush_cache_all()
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#define flush_icache_user_range(vma,pg,adr,len) _flush_cache_all()
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#define flush_cache_sigtramp(addr) _flush_cache_all()
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#else
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#define flush_cache_all() do { } while (0)
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#define flush_cache_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) do { } while (0)
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#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
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#define flush_dcache_page(page) do { } while (0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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#define flush_icache_range(start, end) do { } while (0)
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#define flush_icache_page(vma,pg) do { } while (0)
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#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
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#define flush_cache_sigtramp(addr) do { } while (0)
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#endif /* CONFIG_CHIP_* */
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#define flush_cache_vmap(start, end) do { } while (0)
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#define flush_cache_vunmap(start, end) do { } while (0)
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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memcpy(dst, src, len); \
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flush_icache_user_range(vma, page, vaddr, len); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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memcpy(dst, src, len)
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#endif /* _ASM_M32R_CACHEFLUSH_H */
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