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![Andrew Lunn](/assets/img/avatar_default.png)
An SFP module may have a link up/down status pin which can be connection to a GPIO line of the host. Add support for reading such an GPIO in the fixed_phy driver. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
646 lines
16 KiB
C
646 lines
16 KiB
C
/*
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* Broadcom GENET MDIO routines
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*
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* Copyright (c) 2014 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/types.h>
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#include <linux/delay.h>
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#include <linux/wait.h>
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#include <linux/mii.h>
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#include <linux/ethtool.h>
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#include <linux/bitops.h>
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#include <linux/netdevice.h>
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#include <linux/platform_device.h>
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#include <linux/phy.h>
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#include <linux/phy_fixed.h>
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#include <linux/brcmphy.h>
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#include <linux/of.h>
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#include <linux/of_net.h>
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#include <linux/of_mdio.h>
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#include <linux/platform_data/bcmgenet.h>
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#include "bcmgenet.h"
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/* read a value from the MII */
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static int bcmgenet_mii_read(struct mii_bus *bus, int phy_id, int location)
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{
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int ret;
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struct net_device *dev = bus->priv;
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struct bcmgenet_priv *priv = netdev_priv(dev);
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u32 reg;
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bcmgenet_umac_writel(priv, (MDIO_RD | (phy_id << MDIO_PMD_SHIFT) |
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(location << MDIO_REG_SHIFT)), UMAC_MDIO_CMD);
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/* Start MDIO transaction*/
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reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
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reg |= MDIO_START_BUSY;
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bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
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wait_event_timeout(priv->wq,
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!(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
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& MDIO_START_BUSY),
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HZ / 100);
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ret = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
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/* Some broken devices are known not to release the line during
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* turn-around, e.g: Broadcom BCM53125 external switches, so check for
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* that condition here and ignore the MDIO controller read failure
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* indication.
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*/
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if (!(bus->phy_ignore_ta_mask & 1 << phy_id) && (ret & MDIO_READ_FAIL))
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return -EIO;
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return ret & 0xffff;
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}
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/* write a value to the MII */
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static int bcmgenet_mii_write(struct mii_bus *bus, int phy_id,
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int location, u16 val)
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{
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struct net_device *dev = bus->priv;
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struct bcmgenet_priv *priv = netdev_priv(dev);
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u32 reg;
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bcmgenet_umac_writel(priv, (MDIO_WR | (phy_id << MDIO_PMD_SHIFT) |
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(location << MDIO_REG_SHIFT) | (0xffff & val)),
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UMAC_MDIO_CMD);
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reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
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reg |= MDIO_START_BUSY;
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bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
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wait_event_timeout(priv->wq,
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!(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) &
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MDIO_START_BUSY),
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HZ / 100);
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return 0;
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}
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/* setup netdev link state when PHY link status change and
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* update UMAC and RGMII block when link up
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*/
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void bcmgenet_mii_setup(struct net_device *dev)
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{
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struct bcmgenet_priv *priv = netdev_priv(dev);
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struct phy_device *phydev = priv->phydev;
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u32 reg, cmd_bits = 0;
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bool status_changed = false;
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if (priv->old_link != phydev->link) {
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status_changed = true;
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priv->old_link = phydev->link;
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}
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if (phydev->link) {
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/* check speed/duplex/pause changes */
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if (priv->old_speed != phydev->speed) {
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status_changed = true;
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priv->old_speed = phydev->speed;
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}
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if (priv->old_duplex != phydev->duplex) {
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status_changed = true;
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priv->old_duplex = phydev->duplex;
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}
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if (priv->old_pause != phydev->pause) {
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status_changed = true;
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priv->old_pause = phydev->pause;
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}
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/* done if nothing has changed */
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if (!status_changed)
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return;
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/* speed */
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if (phydev->speed == SPEED_1000)
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cmd_bits = UMAC_SPEED_1000;
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else if (phydev->speed == SPEED_100)
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cmd_bits = UMAC_SPEED_100;
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else
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cmd_bits = UMAC_SPEED_10;
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cmd_bits <<= CMD_SPEED_SHIFT;
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/* duplex */
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if (phydev->duplex != DUPLEX_FULL)
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cmd_bits |= CMD_HD_EN;
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/* pause capability */
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if (!phydev->pause)
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cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
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/*
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* Program UMAC and RGMII block based on established
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* link speed, duplex, and pause. The speed set in
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* umac->cmd tell RGMII block which clock to use for
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* transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
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* Receive clock is provided by the PHY.
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*/
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reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
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reg &= ~OOB_DISABLE;
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reg |= RGMII_LINK;
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bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
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reg = bcmgenet_umac_readl(priv, UMAC_CMD);
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reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
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CMD_HD_EN |
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CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
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reg |= cmd_bits;
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bcmgenet_umac_writel(priv, reg, UMAC_CMD);
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} else {
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/* done if nothing has changed */
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if (!status_changed)
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return;
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/* needed for MoCA fixed PHY to reflect correct link status */
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netif_carrier_off(dev);
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}
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phy_print_status(phydev);
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}
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static int bcmgenet_fixed_phy_link_update(struct net_device *dev,
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struct fixed_phy_status *status)
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{
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if (dev && dev->phydev && status)
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status->link = dev->phydev->link;
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return 0;
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}
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void bcmgenet_phy_power_set(struct net_device *dev, bool enable)
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{
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struct bcmgenet_priv *priv = netdev_priv(dev);
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u32 reg = 0;
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/* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
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if (!GENET_IS_V4(priv))
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return;
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reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
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if (enable) {
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reg &= ~EXT_CK25_DIS;
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bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
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mdelay(1);
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reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN);
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reg |= EXT_GPHY_RESET;
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bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
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mdelay(1);
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reg &= ~EXT_GPHY_RESET;
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} else {
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reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | EXT_GPHY_RESET;
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bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
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mdelay(1);
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reg |= EXT_CK25_DIS;
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}
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bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
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udelay(60);
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}
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static void bcmgenet_internal_phy_setup(struct net_device *dev)
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{
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struct bcmgenet_priv *priv = netdev_priv(dev);
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u32 reg;
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/* Power up PHY */
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bcmgenet_phy_power_set(dev, true);
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/* enable APD */
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reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
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reg |= EXT_PWR_DN_EN_LD;
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bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
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}
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static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
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{
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u32 reg;
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/* Speed settings are set in bcmgenet_mii_setup() */
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reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL);
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reg |= LED_ACT_SOURCE_MAC;
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bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL);
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if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
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fixed_phy_set_link_update(priv->phydev,
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bcmgenet_fixed_phy_link_update);
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}
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int bcmgenet_mii_config(struct net_device *dev)
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{
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struct bcmgenet_priv *priv = netdev_priv(dev);
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struct phy_device *phydev = priv->phydev;
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struct device *kdev = &priv->pdev->dev;
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const char *phy_name = NULL;
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u32 id_mode_dis = 0;
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u32 port_ctrl;
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u32 reg;
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priv->ext_phy = !priv->internal_phy &&
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(priv->phy_interface != PHY_INTERFACE_MODE_MOCA);
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if (priv->internal_phy)
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priv->phy_interface = PHY_INTERFACE_MODE_NA;
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switch (priv->phy_interface) {
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case PHY_INTERFACE_MODE_NA:
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case PHY_INTERFACE_MODE_MOCA:
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/* Irrespective of the actually configured PHY speed (100 or
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* 1000) GENETv4 only has an internal GPHY so we will just end
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* up masking the Gigabit features from what we support, not
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* switching to the EPHY
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*/
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if (GENET_IS_V4(priv))
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port_ctrl = PORT_MODE_INT_GPHY;
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else
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port_ctrl = PORT_MODE_INT_EPHY;
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bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
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if (priv->internal_phy) {
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phy_name = "internal PHY";
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bcmgenet_internal_phy_setup(dev);
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} else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
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phy_name = "MoCA";
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bcmgenet_moca_phy_setup(priv);
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}
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break;
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case PHY_INTERFACE_MODE_MII:
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phy_name = "external MII";
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phydev->supported &= PHY_BASIC_FEATURES;
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bcmgenet_sys_writel(priv,
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PORT_MODE_EXT_EPHY, SYS_PORT_CTRL);
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break;
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case PHY_INTERFACE_MODE_REVMII:
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phy_name = "external RvMII";
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/* of_mdiobus_register took care of reading the 'max-speed'
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* PHY property for us, effectively limiting the PHY supported
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* capabilities, use that knowledge to also configure the
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* Reverse MII interface correctly.
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*/
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if ((priv->phydev->supported & PHY_BASIC_FEATURES) ==
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PHY_BASIC_FEATURES)
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port_ctrl = PORT_MODE_EXT_RVMII_25;
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else
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port_ctrl = PORT_MODE_EXT_RVMII_50;
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bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
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break;
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case PHY_INTERFACE_MODE_RGMII:
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/* RGMII_NO_ID: TXC transitions at the same time as TXD
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* (requires PCB or receiver-side delay)
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* RGMII: Add 2ns delay on TXC (90 degree shift)
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*
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* ID is implicitly disabled for 100Mbps (RG)MII operation.
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*/
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id_mode_dis = BIT(16);
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/* fall through */
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case PHY_INTERFACE_MODE_RGMII_TXID:
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if (id_mode_dis)
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phy_name = "external RGMII (no delay)";
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else
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phy_name = "external RGMII (TX delay)";
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bcmgenet_sys_writel(priv,
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PORT_MODE_EXT_GPHY, SYS_PORT_CTRL);
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break;
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default:
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dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
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return -EINVAL;
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}
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/* This is an external PHY (xMII), so we need to enable the RGMII
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* block for the interface to work
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*/
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if (priv->ext_phy) {
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reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
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reg |= RGMII_MODE_EN | id_mode_dis;
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bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
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}
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dev_info_once(kdev, "configuring instance for %s\n", phy_name);
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return 0;
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}
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int bcmgenet_mii_probe(struct net_device *dev)
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{
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struct bcmgenet_priv *priv = netdev_priv(dev);
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struct device_node *dn = priv->pdev->dev.of_node;
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struct phy_device *phydev;
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u32 phy_flags;
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int ret;
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/* Communicate the integrated PHY revision */
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phy_flags = priv->gphy_rev;
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/* Initialize link state variables that bcmgenet_mii_setup() uses */
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priv->old_link = -1;
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priv->old_speed = -1;
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priv->old_duplex = -1;
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priv->old_pause = -1;
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if (dn) {
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phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,
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phy_flags, priv->phy_interface);
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if (!phydev) {
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pr_err("could not attach to PHY\n");
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return -ENODEV;
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}
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} else {
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phydev = priv->phydev;
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phydev->dev_flags = phy_flags;
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ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup,
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priv->phy_interface);
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if (ret) {
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pr_err("could not attach to PHY\n");
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return -ENODEV;
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}
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}
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priv->phydev = phydev;
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/* Configure port multiplexer based on what the probed PHY device since
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* reading the 'max-speed' property determines the maximum supported
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* PHY speed which is needed for bcmgenet_mii_config() to configure
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* things appropriately.
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*/
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ret = bcmgenet_mii_config(dev);
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if (ret) {
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phy_disconnect(priv->phydev);
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return ret;
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}
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phydev->advertising = phydev->supported;
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/* The internal PHY has its link interrupts routed to the
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* Ethernet MAC ISRs
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*/
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if (priv->internal_phy)
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priv->mii_bus->irq[phydev->addr] = PHY_IGNORE_INTERRUPT;
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else
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priv->mii_bus->irq[phydev->addr] = PHY_POLL;
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return 0;
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}
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/* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with
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* their internal MDIO management controller making them fail to successfully
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* be read from or written to for the first transaction. We insert a dummy
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* BMSR read here to make sure that phy_get_device() and get_phy_id() can
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* correctly read the PHY MII_PHYSID1/2 registers and successfully register a
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* PHY device for this peripheral.
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*
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* Once the PHY driver is registered, we can workaround subsequent reads from
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* there (e.g: during system-wide power management).
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*
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* bus->reset is invoked before mdiobus_scan during mdiobus_register and is
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* therefore the right location to stick that workaround. Since we do not want
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* to read from non-existing PHYs, we either use bus->phy_mask or do a manual
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* Device Tree scan to limit the search area.
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*/
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static int bcmgenet_mii_bus_reset(struct mii_bus *bus)
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{
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struct net_device *dev = bus->priv;
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struct bcmgenet_priv *priv = netdev_priv(dev);
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struct device_node *np = priv->mdio_dn;
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struct device_node *child = NULL;
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u32 read_mask = 0;
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int addr = 0;
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if (!np) {
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read_mask = 1 << priv->phy_addr;
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} else {
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for_each_available_child_of_node(np, child) {
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addr = of_mdio_parse_addr(&dev->dev, child);
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if (addr < 0)
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continue;
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read_mask |= 1 << addr;
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}
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}
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for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
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if (read_mask & 1 << addr) {
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dev_dbg(&dev->dev, "Workaround for PHY @ %d\n", addr);
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mdiobus_read(bus, addr, MII_BMSR);
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}
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}
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return 0;
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}
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static int bcmgenet_mii_alloc(struct bcmgenet_priv *priv)
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{
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struct mii_bus *bus;
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if (priv->mii_bus)
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return 0;
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priv->mii_bus = mdiobus_alloc();
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if (!priv->mii_bus) {
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pr_err("failed to allocate\n");
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return -ENOMEM;
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}
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bus = priv->mii_bus;
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bus->priv = priv->dev;
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bus->name = "bcmgenet MII bus";
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bus->parent = &priv->pdev->dev;
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bus->read = bcmgenet_mii_read;
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bus->write = bcmgenet_mii_write;
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bus->reset = bcmgenet_mii_bus_reset;
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snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d",
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priv->pdev->name, priv->pdev->id);
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bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
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if (!bus->irq) {
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mdiobus_free(priv->mii_bus);
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return -ENOMEM;
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}
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return 0;
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}
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static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
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{
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struct device_node *dn = priv->pdev->dev.of_node;
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struct device *kdev = &priv->pdev->dev;
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const char *phy_mode_str = NULL;
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struct phy_device *phydev = NULL;
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char *compat;
|
|
int phy_mode;
|
|
int ret;
|
|
|
|
compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
|
|
if (!compat)
|
|
return -ENOMEM;
|
|
|
|
priv->mdio_dn = of_find_compatible_node(dn, NULL, compat);
|
|
kfree(compat);
|
|
if (!priv->mdio_dn) {
|
|
dev_err(kdev, "unable to find MDIO bus node\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
ret = of_mdiobus_register(priv->mii_bus, priv->mdio_dn);
|
|
if (ret) {
|
|
dev_err(kdev, "failed to register MDIO bus\n");
|
|
return ret;
|
|
}
|
|
|
|
/* Fetch the PHY phandle */
|
|
priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);
|
|
|
|
/* In the case of a fixed PHY, the DT node associated
|
|
* to the PHY is the Ethernet MAC DT node.
|
|
*/
|
|
if (!priv->phy_dn && of_phy_is_fixed_link(dn)) {
|
|
ret = of_phy_register_fixed_link(dn);
|
|
if (ret)
|
|
return ret;
|
|
|
|
priv->phy_dn = of_node_get(dn);
|
|
}
|
|
|
|
/* Get the link mode */
|
|
phy_mode = of_get_phy_mode(dn);
|
|
priv->phy_interface = phy_mode;
|
|
|
|
/* We need to specifically look up whether this PHY interface is internal
|
|
* or not *before* we even try to probe the PHY driver over MDIO as we
|
|
* may have shut down the internal PHY for power saving purposes.
|
|
*/
|
|
if (phy_mode < 0) {
|
|
ret = of_property_read_string(dn, "phy-mode", &phy_mode_str);
|
|
if (ret < 0) {
|
|
dev_err(kdev, "invalid PHY mode property\n");
|
|
return ret;
|
|
}
|
|
|
|
priv->phy_interface = PHY_INTERFACE_MODE_NA;
|
|
if (!strcasecmp(phy_mode_str, "internal"))
|
|
priv->internal_phy = true;
|
|
}
|
|
|
|
/* Make sure we initialize MoCA PHYs with a link down */
|
|
if (phy_mode == PHY_INTERFACE_MODE_MOCA) {
|
|
phydev = of_phy_find_device(dn);
|
|
if (phydev)
|
|
phydev->link = 0;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv)
|
|
{
|
|
struct device *kdev = &priv->pdev->dev;
|
|
struct bcmgenet_platform_data *pd = kdev->platform_data;
|
|
struct mii_bus *mdio = priv->mii_bus;
|
|
struct phy_device *phydev;
|
|
int ret;
|
|
|
|
if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
|
|
/*
|
|
* Internal or external PHY with MDIO access
|
|
*/
|
|
if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
|
|
mdio->phy_mask = ~(1 << pd->phy_address);
|
|
else
|
|
mdio->phy_mask = 0;
|
|
|
|
ret = mdiobus_register(mdio);
|
|
if (ret) {
|
|
dev_err(kdev, "failed to register MDIO bus\n");
|
|
return ret;
|
|
}
|
|
|
|
if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
|
|
phydev = mdio->phy_map[pd->phy_address];
|
|
else
|
|
phydev = phy_find_first(mdio);
|
|
|
|
if (!phydev) {
|
|
dev_err(kdev, "failed to register PHY device\n");
|
|
mdiobus_unregister(mdio);
|
|
return -ENODEV;
|
|
}
|
|
} else {
|
|
/*
|
|
* MoCA port or no MDIO access.
|
|
* Use fixed PHY to represent the link layer.
|
|
*/
|
|
struct fixed_phy_status fphy_status = {
|
|
.link = 1,
|
|
.speed = pd->phy_speed,
|
|
.duplex = pd->phy_duplex,
|
|
.pause = 0,
|
|
.asym_pause = 0,
|
|
};
|
|
|
|
phydev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
|
|
if (!phydev || IS_ERR(phydev)) {
|
|
dev_err(kdev, "failed to register fixed PHY device\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* Make sure we initialize MoCA PHYs with a link down */
|
|
phydev->link = 0;
|
|
|
|
}
|
|
|
|
priv->phydev = phydev;
|
|
priv->phy_interface = pd->phy_interface;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv)
|
|
{
|
|
struct device_node *dn = priv->pdev->dev.of_node;
|
|
|
|
if (dn)
|
|
return bcmgenet_mii_of_init(priv);
|
|
else
|
|
return bcmgenet_mii_pd_init(priv);
|
|
}
|
|
|
|
int bcmgenet_mii_init(struct net_device *dev)
|
|
{
|
|
struct bcmgenet_priv *priv = netdev_priv(dev);
|
|
int ret;
|
|
|
|
ret = bcmgenet_mii_alloc(priv);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = bcmgenet_mii_bus_init(priv);
|
|
if (ret)
|
|
goto out;
|
|
|
|
return 0;
|
|
|
|
out:
|
|
of_node_put(priv->phy_dn);
|
|
mdiobus_unregister(priv->mii_bus);
|
|
kfree(priv->mii_bus->irq);
|
|
mdiobus_free(priv->mii_bus);
|
|
return ret;
|
|
}
|
|
|
|
void bcmgenet_mii_exit(struct net_device *dev)
|
|
{
|
|
struct bcmgenet_priv *priv = netdev_priv(dev);
|
|
|
|
of_node_put(priv->phy_dn);
|
|
mdiobus_unregister(priv->mii_bus);
|
|
kfree(priv->mii_bus->irq);
|
|
mdiobus_free(priv->mii_bus);
|
|
}
|