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![Vineet Gupta](/assets/img/avatar_default.png)
ARCv2 MMU is software walked and Linux implements 2 levels of paging: pgd/pte. Forthcoming hw will have multiple levels, so this change preps mm code for same. It is also fun to try multi levels even on soft-walked code to ensure generic mm code is robust to handle. overview ________ 2 levels {pgd, pte} : pmd is folded but pmd_* macros are valid and operate on pgd 3 levels {pgd, pmd, pte}: - pud is folded and pud_* macros point to pgd - pmd_* macros operate on actual pmd code changes ____________ 1. #include <asm-generic/pgtable-nopud.h> 2. Define CONFIG_PGTABLE_LEVELS 3 3a. Define PMD_SHIFT, PMD_SIZE, PMD_MASK, pmd_t 3b. Define pmd_val() which actually deals with pmd (pmd_offset(), pmd_index() are provided by generic code) 3c. pmd_alloc_one()/pmd_free() also provided by generic code (pmd_populate/pmd_free already exist) 4. Define pud_none(), pud_bad() macros based on generic pud_val() which internally pertains to pgd now. 4b. define pud_populate() to just setup pgd Acked-by: Mike Rapoport <rppt@linux.ibm.com> Signed-off-by: Vineet Gupta <vgupta@kernel.org>
780 lines
21 KiB
C
780 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* TLB Management (flush/create/diagnostics) for MMUv3 and MMUv4
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*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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*/
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#include <linux/module.h>
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#include <linux/bug.h>
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#include <linux/mm_types.h>
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#include <asm/arcregs.h>
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#include <asm/setup.h>
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#include <asm/mmu_context.h>
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#include <asm/mmu.h>
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/* A copy of the ASID from the PID reg is kept in asid_cache */
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DEFINE_PER_CPU(unsigned int, asid_cache) = MM_CTXT_FIRST_CYCLE;
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static int __read_mostly pae_exists;
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/*
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* Utility Routine to erase a J-TLB entry
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* Caller needs to setup Index Reg (manually or via getIndex)
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*/
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static inline void __tlb_entry_erase(void)
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{
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write_aux_reg(ARC_REG_TLBPD1, 0);
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if (is_pae40_enabled())
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write_aux_reg(ARC_REG_TLBPD1HI, 0);
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write_aux_reg(ARC_REG_TLBPD0, 0);
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write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
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}
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static void utlb_invalidate(void)
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{
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write_aux_reg(ARC_REG_TLBCOMMAND, TLBIVUTLB);
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}
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#ifdef CONFIG_ARC_MMU_V3
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static inline unsigned int tlb_entry_lkup(unsigned long vaddr_n_asid)
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{
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unsigned int idx;
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write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid);
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write_aux_reg(ARC_REG_TLBCOMMAND, TLBProbe);
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idx = read_aux_reg(ARC_REG_TLBINDEX);
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return idx;
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}
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static void tlb_entry_erase(unsigned int vaddr_n_asid)
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{
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unsigned int idx;
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/* Locate the TLB entry for this vaddr + ASID */
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idx = tlb_entry_lkup(vaddr_n_asid);
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/* No error means entry found, zero it out */
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if (likely(!(idx & TLB_LKUP_ERR))) {
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__tlb_entry_erase();
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} else {
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/* Duplicate entry error */
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WARN(idx == TLB_DUP_ERR, "Probe returned Dup PD for %x\n",
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vaddr_n_asid);
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}
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}
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static void tlb_entry_insert(unsigned int pd0, phys_addr_t pd1)
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{
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unsigned int idx;
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/*
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* First verify if entry for this vaddr+ASID already exists
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* This also sets up PD0 (vaddr, ASID..) for final commit
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*/
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idx = tlb_entry_lkup(pd0);
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/*
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* If Not already present get a free slot from MMU.
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* Otherwise, Probe would have located the entry and set INDEX Reg
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* with existing location. This will cause Write CMD to over-write
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* existing entry with new PD0 and PD1
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*/
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if (likely(idx & TLB_LKUP_ERR))
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write_aux_reg(ARC_REG_TLBCOMMAND, TLBGetIndex);
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/* setup the other half of TLB entry (pfn, rwx..) */
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write_aux_reg(ARC_REG_TLBPD1, pd1);
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/*
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* Commit the Entry to MMU
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* It doesn't sound safe to use the TLBWriteNI cmd here
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* which doesn't flush uTLBs. I'd rather be safe than sorry.
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*/
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write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
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}
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#else /* MMUv4 */
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static void tlb_entry_erase(unsigned int vaddr_n_asid)
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{
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write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid | _PAGE_PRESENT);
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write_aux_reg(ARC_REG_TLBCOMMAND, TLBDeleteEntry);
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}
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static void tlb_entry_insert(unsigned int pd0, phys_addr_t pd1)
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{
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write_aux_reg(ARC_REG_TLBPD0, pd0);
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if (!is_pae40_enabled()) {
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write_aux_reg(ARC_REG_TLBPD1, pd1);
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} else {
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write_aux_reg(ARC_REG_TLBPD1, pd1 & 0xFFFFFFFF);
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write_aux_reg(ARC_REG_TLBPD1HI, (u64)pd1 >> 32);
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}
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write_aux_reg(ARC_REG_TLBCOMMAND, TLBInsertEntry);
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}
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#endif
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/*
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* Un-conditionally (without lookup) erase the entire MMU contents
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*/
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noinline void local_flush_tlb_all(void)
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{
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struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
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unsigned long flags;
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unsigned int entry;
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int num_tlb = mmu->sets * mmu->ways;
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local_irq_save(flags);
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/* Load PD0 and PD1 with template for a Blank Entry */
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write_aux_reg(ARC_REG_TLBPD1, 0);
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if (is_pae40_enabled())
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write_aux_reg(ARC_REG_TLBPD1HI, 0);
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write_aux_reg(ARC_REG_TLBPD0, 0);
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for (entry = 0; entry < num_tlb; entry++) {
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/* write this entry to the TLB */
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write_aux_reg(ARC_REG_TLBINDEX, entry);
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write_aux_reg(ARC_REG_TLBCOMMAND, TLBWriteNI);
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}
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if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE)) {
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const int stlb_idx = 0x800;
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/* Blank sTLB entry */
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write_aux_reg(ARC_REG_TLBPD0, _PAGE_HW_SZ);
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for (entry = stlb_idx; entry < stlb_idx + 16; entry++) {
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write_aux_reg(ARC_REG_TLBINDEX, entry);
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write_aux_reg(ARC_REG_TLBCOMMAND, TLBWriteNI);
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}
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}
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utlb_invalidate();
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local_irq_restore(flags);
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}
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/*
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* Flush the entire MM for userland. The fastest way is to move to Next ASID
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*/
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noinline void local_flush_tlb_mm(struct mm_struct *mm)
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{
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/*
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* Small optimisation courtesy IA64
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* flush_mm called during fork,exit,munmap etc, multiple times as well.
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* Only for fork( ) do we need to move parent to a new MMU ctxt,
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* all other cases are NOPs, hence this check.
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*/
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if (atomic_read(&mm->mm_users) == 0)
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return;
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/*
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* - Move to a new ASID, but only if the mm is still wired in
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* (Android Binder ended up calling this for vma->mm != tsk->mm,
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* causing h/w - s/w ASID to get out of sync)
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* - Also get_new_mmu_context() new implementation allocates a new
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* ASID only if it is not allocated already - so unallocate first
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*/
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destroy_context(mm);
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if (current->mm == mm)
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get_new_mmu_context(mm);
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}
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/*
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* Flush a Range of TLB entries for userland.
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* @start is inclusive, while @end is exclusive
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* Difference between this and Kernel Range Flush is
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* -Here the fastest way (if range is too large) is to move to next ASID
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* without doing any explicit Shootdown
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* -In case of kernel Flush, entry has to be shot down explicitly
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*/
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void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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const unsigned int cpu = smp_processor_id();
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unsigned long flags;
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/* If range @start to @end is more than 32 TLB entries deep,
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* its better to move to a new ASID rather than searching for
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* individual entries and then shooting them down
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*
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* The calc above is rough, doesn't account for unaligned parts,
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* since this is heuristics based anyways
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*/
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if (unlikely((end - start) >= PAGE_SIZE * 32)) {
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local_flush_tlb_mm(vma->vm_mm);
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return;
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}
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/*
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* @start moved to page start: this alone suffices for checking
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* loop end condition below, w/o need for aligning @end to end
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* e.g. 2000 to 4001 will anyhow loop twice
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*/
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start &= PAGE_MASK;
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local_irq_save(flags);
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if (asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID) {
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while (start < end) {
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tlb_entry_erase(start | hw_pid(vma->vm_mm, cpu));
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start += PAGE_SIZE;
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}
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}
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local_irq_restore(flags);
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}
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/* Flush the kernel TLB entries - vmalloc/modules (Global from MMU perspective)
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* @start, @end interpreted as kvaddr
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* Interestingly, shared TLB entries can also be flushed using just
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* @start,@end alone (interpreted as user vaddr), although technically SASID
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* is also needed. However our smart TLbProbe lookup takes care of that.
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*/
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void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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unsigned long flags;
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/* exactly same as above, except for TLB entry not taking ASID */
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if (unlikely((end - start) >= PAGE_SIZE * 32)) {
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local_flush_tlb_all();
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return;
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}
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start &= PAGE_MASK;
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local_irq_save(flags);
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while (start < end) {
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tlb_entry_erase(start);
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start += PAGE_SIZE;
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}
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local_irq_restore(flags);
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}
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/*
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* Delete TLB entry in MMU for a given page (??? address)
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* NOTE One TLB entry contains translation for single PAGE
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*/
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void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
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{
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const unsigned int cpu = smp_processor_id();
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unsigned long flags;
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/* Note that it is critical that interrupts are DISABLED between
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* checking the ASID and using it flush the TLB entry
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*/
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local_irq_save(flags);
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if (asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID) {
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tlb_entry_erase((page & PAGE_MASK) | hw_pid(vma->vm_mm, cpu));
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}
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local_irq_restore(flags);
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}
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#ifdef CONFIG_SMP
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struct tlb_args {
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struct vm_area_struct *ta_vma;
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unsigned long ta_start;
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unsigned long ta_end;
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};
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static inline void ipi_flush_tlb_page(void *arg)
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{
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struct tlb_args *ta = arg;
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local_flush_tlb_page(ta->ta_vma, ta->ta_start);
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}
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static inline void ipi_flush_tlb_range(void *arg)
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{
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struct tlb_args *ta = arg;
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local_flush_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end);
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}
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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static inline void ipi_flush_pmd_tlb_range(void *arg)
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{
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struct tlb_args *ta = arg;
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local_flush_pmd_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end);
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}
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#endif
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static inline void ipi_flush_tlb_kernel_range(void *arg)
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{
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struct tlb_args *ta = (struct tlb_args *)arg;
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local_flush_tlb_kernel_range(ta->ta_start, ta->ta_end);
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}
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void flush_tlb_all(void)
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{
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on_each_cpu((smp_call_func_t)local_flush_tlb_all, NULL, 1);
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}
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void flush_tlb_mm(struct mm_struct *mm)
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{
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on_each_cpu_mask(mm_cpumask(mm), (smp_call_func_t)local_flush_tlb_mm,
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mm, 1);
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}
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void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
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{
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struct tlb_args ta = {
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.ta_vma = vma,
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.ta_start = uaddr
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};
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on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_page, &ta, 1);
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}
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void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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struct tlb_args ta = {
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.ta_vma = vma,
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.ta_start = start,
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.ta_end = end
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};
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on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_range, &ta, 1);
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}
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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struct tlb_args ta = {
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.ta_vma = vma,
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.ta_start = start,
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.ta_end = end
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};
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on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_pmd_tlb_range, &ta, 1);
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}
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#endif
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void flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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struct tlb_args ta = {
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.ta_start = start,
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.ta_end = end
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};
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on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1);
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}
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#endif
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/*
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* Routine to create a TLB entry
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*/
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void create_tlb(struct vm_area_struct *vma, unsigned long vaddr, pte_t *ptep)
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{
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unsigned long flags;
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unsigned int asid_or_sasid, rwx;
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unsigned long pd0;
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phys_addr_t pd1;
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/*
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* create_tlb() assumes that current->mm == vma->mm, since
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* -it ASID for TLB entry is fetched from MMU ASID reg (valid for curr)
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* -completes the lazy write to SASID reg (again valid for curr tsk)
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*
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* Removing the assumption involves
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* -Using vma->mm->context{ASID,SASID}, as opposed to MMU reg.
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* -More importantly it makes this handler inconsistent with fast-path
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* TLB Refill handler which always deals with "current"
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*
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* Lets see the use cases when current->mm != vma->mm and we land here
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* 1. execve->copy_strings()->__get_user_pages->handle_mm_fault
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* Here VM wants to pre-install a TLB entry for user stack while
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* current->mm still points to pre-execve mm (hence the condition).
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* However the stack vaddr is soon relocated (randomization) and
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* move_page_tables() tries to undo that TLB entry.
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* Thus not creating TLB entry is not any worse.
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*
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* 2. ptrace(POKETEXT) causes a CoW - debugger(current) inserting a
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* breakpoint in debugged task. Not creating a TLB now is not
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* performance critical.
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*
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* Both the cases above are not good enough for code churn.
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*/
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if (current->active_mm != vma->vm_mm)
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return;
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local_irq_save(flags);
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vaddr &= PAGE_MASK;
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/* update this PTE credentials */
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pte_val(*ptep) |= (_PAGE_PRESENT | _PAGE_ACCESSED);
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/* Create HW TLB(PD0,PD1) from PTE */
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/* ASID for this task */
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asid_or_sasid = read_aux_reg(ARC_REG_PID) & 0xff;
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pd0 = vaddr | asid_or_sasid | (pte_val(*ptep) & PTE_BITS_IN_PD0);
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/*
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* ARC MMU provides fully orthogonal access bits for K/U mode,
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* however Linux only saves 1 set to save PTE real-estate
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* Here we convert 3 PTE bits into 6 MMU bits:
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* -Kernel only entries have Kr Kw Kx 0 0 0
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* -User entries have mirrored K and U bits
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*/
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rwx = pte_val(*ptep) & PTE_BITS_RWX;
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if (pte_val(*ptep) & _PAGE_GLOBAL)
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rwx <<= 3; /* r w x => Kr Kw Kx 0 0 0 */
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else
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rwx |= (rwx << 3); /* r w x => Kr Kw Kx Ur Uw Ux */
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pd1 = rwx | (pte_val(*ptep) & PTE_BITS_NON_RWX_IN_PD1);
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tlb_entry_insert(pd0, pd1);
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local_irq_restore(flags);
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}
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/*
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* Called at the end of pagefault, for a userspace mapped page
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* -pre-install the corresponding TLB entry into MMU
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* -Finalize the delayed D-cache flush of kernel mapping of page due to
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* flush_dcache_page(), copy_user_page()
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*
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* Note that flush (when done) involves both WBACK - so physical page is
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* in sync as well as INV - so any non-congruent aliases don't remain
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*/
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void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
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pte_t *ptep)
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{
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unsigned long vaddr = vaddr_unaligned & PAGE_MASK;
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phys_addr_t paddr = pte_val(*ptep) & PAGE_MASK_PHYS;
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struct page *page = pfn_to_page(pte_pfn(*ptep));
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create_tlb(vma, vaddr, ptep);
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if (page == ZERO_PAGE(0)) {
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return;
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}
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|
|
|
/*
|
|
* Exec page : Independent of aliasing/page-color considerations,
|
|
* since icache doesn't snoop dcache on ARC, any dirty
|
|
* K-mapping of a code page needs to be wback+inv so that
|
|
* icache fetch by userspace sees code correctly.
|
|
* !EXEC page: If K-mapping is NOT congruent to U-mapping, flush it
|
|
* so userspace sees the right data.
|
|
* (Avoids the flush for Non-exec + congruent mapping case)
|
|
*/
|
|
if ((vma->vm_flags & VM_EXEC) ||
|
|
addr_not_cache_congruent(paddr, vaddr)) {
|
|
|
|
int dirty = !test_and_set_bit(PG_dc_clean, &page->flags);
|
|
if (dirty) {
|
|
/* wback + inv dcache lines (K-mapping) */
|
|
__flush_dcache_page(paddr, paddr);
|
|
|
|
/* invalidate any existing icache lines (U-mapping) */
|
|
if (vma->vm_flags & VM_EXEC)
|
|
__inv_icache_page(paddr, vaddr);
|
|
}
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
|
|
|
|
/*
|
|
* MMUv4 in HS38x cores supports Super Pages which are basis for Linux THP
|
|
* support.
|
|
*
|
|
* Normal and Super pages can co-exist (ofcourse not overlap) in TLB with a
|
|
* new bit "SZ" in TLB page descriptor to distinguish between them.
|
|
* Super Page size is configurable in hardware (4K to 16M), but fixed once
|
|
* RTL builds.
|
|
*
|
|
* The exact THP size a Linux configuration will support is a function of:
|
|
* - MMU page size (typical 8K, RTL fixed)
|
|
* - software page walker address split between PGD:PTE:PFN (typical
|
|
* 11:8:13, but can be changed with 1 line)
|
|
* So for above default, THP size supported is 8K * (2^8) = 2M
|
|
*
|
|
* Default Page Walker is 2 levels, PGD:PTE:PFN, which in THP regime
|
|
* reduces to 1 level (as PTE is folded into PGD and canonically referred
|
|
* to as PMD).
|
|
* Thus THP PMD accessors are implemented in terms of PTE (just like sparc)
|
|
*/
|
|
|
|
void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
|
|
pmd_t *pmd)
|
|
{
|
|
pte_t pte = __pte(pmd_val(*pmd));
|
|
update_mmu_cache(vma, addr, &pte);
|
|
}
|
|
|
|
void local_flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
|
|
unsigned long end)
|
|
{
|
|
unsigned int cpu;
|
|
unsigned long flags;
|
|
|
|
local_irq_save(flags);
|
|
|
|
cpu = smp_processor_id();
|
|
|
|
if (likely(asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID)) {
|
|
unsigned int asid = hw_pid(vma->vm_mm, cpu);
|
|
|
|
/* No need to loop here: this will always be for 1 Huge Page */
|
|
tlb_entry_erase(start | _PAGE_HW_SZ | asid);
|
|
}
|
|
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
#endif
|
|
|
|
/* Read the Cache Build Configuration Registers, Decode them and save into
|
|
* the cpuinfo structure for later use.
|
|
* No Validation is done here, simply read/convert the BCRs
|
|
*/
|
|
void read_decode_mmu_bcr(void)
|
|
{
|
|
struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
|
|
unsigned int tmp;
|
|
struct bcr_mmu_3 {
|
|
#ifdef CONFIG_CPU_BIG_ENDIAN
|
|
unsigned int ver:8, ways:4, sets:4, res:3, sasid:1, pg_sz:4,
|
|
u_itlb:4, u_dtlb:4;
|
|
#else
|
|
unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, sasid:1, res:3, sets:4,
|
|
ways:4, ver:8;
|
|
#endif
|
|
} *mmu3;
|
|
|
|
struct bcr_mmu_4 {
|
|
#ifdef CONFIG_CPU_BIG_ENDIAN
|
|
unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
|
|
n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;
|
|
#else
|
|
/* DTLB ITLB JES JE JA */
|
|
unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2,
|
|
pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;
|
|
#endif
|
|
} *mmu4;
|
|
|
|
tmp = read_aux_reg(ARC_REG_MMU_BCR);
|
|
mmu->ver = (tmp >> 24);
|
|
|
|
if (is_isa_arcompact() && mmu->ver == 3) {
|
|
mmu3 = (struct bcr_mmu_3 *)&tmp;
|
|
mmu->pg_sz_k = 1 << (mmu3->pg_sz - 1);
|
|
mmu->sets = 1 << mmu3->sets;
|
|
mmu->ways = 1 << mmu3->ways;
|
|
mmu->u_dtlb = mmu3->u_dtlb;
|
|
mmu->u_itlb = mmu3->u_itlb;
|
|
mmu->sasid = mmu3->sasid;
|
|
} else {
|
|
mmu4 = (struct bcr_mmu_4 *)&tmp;
|
|
mmu->pg_sz_k = 1 << (mmu4->sz0 - 1);
|
|
mmu->s_pg_sz_m = 1 << (mmu4->sz1 - 11);
|
|
mmu->sets = 64 << mmu4->n_entry;
|
|
mmu->ways = mmu4->n_ways * 2;
|
|
mmu->u_dtlb = mmu4->u_dtlb * 4;
|
|
mmu->u_itlb = mmu4->u_itlb * 4;
|
|
mmu->sasid = mmu4->sasid;
|
|
pae_exists = mmu->pae = mmu4->pae;
|
|
}
|
|
}
|
|
|
|
char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len)
|
|
{
|
|
int n = 0;
|
|
struct cpuinfo_arc_mmu *p_mmu = &cpuinfo_arc700[cpu_id].mmu;
|
|
char super_pg[64] = "";
|
|
|
|
if (p_mmu->s_pg_sz_m)
|
|
scnprintf(super_pg, 64, "%dM Super Page %s",
|
|
p_mmu->s_pg_sz_m,
|
|
IS_USED_CFG(CONFIG_TRANSPARENT_HUGEPAGE));
|
|
|
|
n += scnprintf(buf + n, len - n,
|
|
"MMU [v%x]\t: %dk PAGE, %s, swalk %d lvl, JTLB %d (%dx%d), uDTLB %d, uITLB %d%s%s\n",
|
|
p_mmu->ver, p_mmu->pg_sz_k, super_pg, CONFIG_PGTABLE_LEVELS,
|
|
p_mmu->sets * p_mmu->ways, p_mmu->sets, p_mmu->ways,
|
|
p_mmu->u_dtlb, p_mmu->u_itlb,
|
|
IS_AVAIL2(p_mmu->pae, ", PAE40 ", CONFIG_ARC_HAS_PAE40));
|
|
|
|
return buf;
|
|
}
|
|
|
|
int pae40_exist_but_not_enab(void)
|
|
{
|
|
return pae_exists && !is_pae40_enabled();
|
|
}
|
|
|
|
void arc_mmu_init(void)
|
|
{
|
|
struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
|
|
char str[256];
|
|
int compat = 0;
|
|
|
|
pr_info("%s", arc_mmu_mumbojumbo(0, str, sizeof(str)));
|
|
|
|
/*
|
|
* Can't be done in processor.h due to header include dependencies
|
|
*/
|
|
BUILD_BUG_ON(!IS_ALIGNED((CONFIG_ARC_KVADDR_SIZE << 20), PMD_SIZE));
|
|
|
|
/*
|
|
* stack top size sanity check,
|
|
* Can't be done in processor.h due to header include dependencies
|
|
*/
|
|
BUILD_BUG_ON(!IS_ALIGNED(STACK_TOP, PMD_SIZE));
|
|
|
|
/*
|
|
* Ensure that MMU features assumed by kernel exist in hardware.
|
|
* - For older ARC700 cpus, only v3 supported
|
|
* - For HS cpus, v4 was baseline and v5 is backwards compatible
|
|
* (will run older software).
|
|
*/
|
|
if (is_isa_arcompact() && mmu->ver == 3)
|
|
compat = 1;
|
|
else if (is_isa_arcv2() && mmu->ver >= 4)
|
|
compat = 1;
|
|
|
|
if (!compat)
|
|
panic("MMU ver %d doesn't match kernel built for\n", mmu->ver);
|
|
|
|
if (mmu->pg_sz_k != TO_KB(PAGE_SIZE))
|
|
panic("MMU pg size != PAGE_SIZE (%luk)\n", TO_KB(PAGE_SIZE));
|
|
|
|
if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE) &&
|
|
mmu->s_pg_sz_m != TO_MB(HPAGE_PMD_SIZE))
|
|
panic("MMU Super pg size != Linux HPAGE_PMD_SIZE (%luM)\n",
|
|
(unsigned long)TO_MB(HPAGE_PMD_SIZE));
|
|
|
|
if (IS_ENABLED(CONFIG_ARC_HAS_PAE40) && !mmu->pae)
|
|
panic("Hardware doesn't support PAE40\n");
|
|
|
|
/* Enable the MMU with ASID 0 */
|
|
mmu_setup_asid(NULL, 0);
|
|
|
|
/* cache the pgd pointer in MMU SCRATCH reg (ARCv2 only) */
|
|
mmu_setup_pgd(NULL, swapper_pg_dir);
|
|
|
|
if (pae40_exist_but_not_enab())
|
|
write_aux_reg(ARC_REG_TLBPD1HI, 0);
|
|
}
|
|
|
|
/*
|
|
* TLB Programmer's Model uses Linear Indexes: 0 to {255, 511} for 128 x {2,4}
|
|
* The mapping is Column-first.
|
|
* --------------------- -----------
|
|
* |way0|way1|way2|way3| |way0|way1|
|
|
* --------------------- -----------
|
|
* [set0] | 0 | 1 | 2 | 3 | | 0 | 1 |
|
|
* [set1] | 4 | 5 | 6 | 7 | | 2 | 3 |
|
|
* ~ ~ ~ ~
|
|
* [set127] | 508| 509| 510| 511| | 254| 255|
|
|
* --------------------- -----------
|
|
* For normal operations we don't(must not) care how above works since
|
|
* MMU cmd getIndex(vaddr) abstracts that out.
|
|
* However for walking WAYS of a SET, we need to know this
|
|
*/
|
|
#define SET_WAY_TO_IDX(mmu, set, way) ((set) * mmu->ways + (way))
|
|
|
|
/* Handling of Duplicate PD (TLB entry) in MMU.
|
|
* -Could be due to buggy customer tapeouts or obscure kernel bugs
|
|
* -MMU complaints not at the time of duplicate PD installation, but at the
|
|
* time of lookup matching multiple ways.
|
|
* -Ideally these should never happen - but if they do - workaround by deleting
|
|
* the duplicate one.
|
|
* -Knob to be verbose abt it.(TODO: hook them up to debugfs)
|
|
*/
|
|
volatile int dup_pd_silent; /* Be silent abt it or complain (default) */
|
|
|
|
void do_tlb_overlap_fault(unsigned long cause, unsigned long address,
|
|
struct pt_regs *regs)
|
|
{
|
|
struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
|
|
unsigned long flags;
|
|
int set, n_ways = mmu->ways;
|
|
|
|
n_ways = min(n_ways, 4);
|
|
BUG_ON(mmu->ways > 4);
|
|
|
|
local_irq_save(flags);
|
|
|
|
/* loop thru all sets of TLB */
|
|
for (set = 0; set < mmu->sets; set++) {
|
|
|
|
int is_valid, way;
|
|
unsigned int pd0[4];
|
|
|
|
/* read out all the ways of current set */
|
|
for (way = 0, is_valid = 0; way < n_ways; way++) {
|
|
write_aux_reg(ARC_REG_TLBINDEX,
|
|
SET_WAY_TO_IDX(mmu, set, way));
|
|
write_aux_reg(ARC_REG_TLBCOMMAND, TLBRead);
|
|
pd0[way] = read_aux_reg(ARC_REG_TLBPD0);
|
|
is_valid |= pd0[way] & _PAGE_PRESENT;
|
|
pd0[way] &= PAGE_MASK;
|
|
}
|
|
|
|
/* If all the WAYS in SET are empty, skip to next SET */
|
|
if (!is_valid)
|
|
continue;
|
|
|
|
/* Scan the set for duplicate ways: needs a nested loop */
|
|
for (way = 0; way < n_ways - 1; way++) {
|
|
|
|
int n;
|
|
|
|
if (!pd0[way])
|
|
continue;
|
|
|
|
for (n = way + 1; n < n_ways; n++) {
|
|
if (pd0[way] != pd0[n])
|
|
continue;
|
|
|
|
if (!dup_pd_silent)
|
|
pr_info("Dup TLB PD0 %08x @ set %d ways %d,%d\n",
|
|
pd0[way], set, way, n);
|
|
|
|
/*
|
|
* clear entry @way and not @n.
|
|
* This is critical to our optimised loop
|
|
*/
|
|
pd0[way] = 0;
|
|
write_aux_reg(ARC_REG_TLBINDEX,
|
|
SET_WAY_TO_IDX(mmu, set, way));
|
|
__tlb_entry_erase();
|
|
}
|
|
}
|
|
}
|
|
|
|
local_irq_restore(flags);
|
|
}
|