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![Rajendra Nayak](/assets/img/avatar_default.png)
The votable alpha PLLs need to have the fsm mode enabled as part of the initialization. The sequence seems to be the same as used by clk-pll, so move the function which does this into a common place and reuse it for the clk-alpha-pll Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
344 lines
8 KiB
C
344 lines
8 KiB
C
/*
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* Copyright (c) 2013, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/bug.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include <asm/div64.h>
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#include "clk-pll.h"
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#include "common.h"
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#define PLL_OUTCTRL BIT(0)
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#define PLL_BYPASSNL BIT(1)
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#define PLL_RESET_N BIT(2)
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static int clk_pll_enable(struct clk_hw *hw)
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{
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struct clk_pll *pll = to_clk_pll(hw);
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int ret;
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u32 mask, val;
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mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
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ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val);
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if (ret)
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return ret;
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/* Skip if already enabled or in FSM mode */
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if ((val & mask) == mask || val & PLL_VOTE_FSM_ENA)
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return 0;
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/* Disable PLL bypass mode. */
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ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,
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PLL_BYPASSNL);
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if (ret)
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return ret;
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/*
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* H/W requires a 5us delay between disabling the bypass and
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* de-asserting the reset. Delay 10us just to be safe.
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*/
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udelay(10);
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/* De-assert active-low PLL reset. */
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ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,
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PLL_RESET_N);
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if (ret)
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return ret;
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/* Wait until PLL is locked. */
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udelay(50);
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/* Enable PLL output. */
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return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,
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PLL_OUTCTRL);
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}
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static void clk_pll_disable(struct clk_hw *hw)
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{
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struct clk_pll *pll = to_clk_pll(hw);
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u32 mask;
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u32 val;
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regmap_read(pll->clkr.regmap, pll->mode_reg, &val);
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/* Skip if in FSM mode */
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if (val & PLL_VOTE_FSM_ENA)
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return;
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mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
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regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0);
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}
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static unsigned long
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clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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struct clk_pll *pll = to_clk_pll(hw);
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u32 l, m, n, config;
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unsigned long rate;
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u64 tmp;
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regmap_read(pll->clkr.regmap, pll->l_reg, &l);
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regmap_read(pll->clkr.regmap, pll->m_reg, &m);
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regmap_read(pll->clkr.regmap, pll->n_reg, &n);
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l &= 0x3ff;
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m &= 0x7ffff;
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n &= 0x7ffff;
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rate = parent_rate * l;
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if (n) {
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tmp = parent_rate;
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tmp *= m;
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do_div(tmp, n);
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rate += tmp;
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}
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if (pll->post_div_width) {
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regmap_read(pll->clkr.regmap, pll->config_reg, &config);
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config >>= pll->post_div_shift;
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config &= BIT(pll->post_div_width) - 1;
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rate /= config + 1;
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}
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return rate;
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}
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static const
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struct pll_freq_tbl *find_freq(const struct pll_freq_tbl *f, unsigned long rate)
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{
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if (!f)
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return NULL;
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for (; f->freq; f++)
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if (rate <= f->freq)
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return f;
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return NULL;
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}
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static int
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clk_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
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{
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struct clk_pll *pll = to_clk_pll(hw);
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const struct pll_freq_tbl *f;
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f = find_freq(pll->freq_tbl, req->rate);
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if (!f)
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req->rate = clk_pll_recalc_rate(hw, req->best_parent_rate);
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else
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req->rate = f->freq;
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return 0;
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}
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static int
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clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long p_rate)
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{
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struct clk_pll *pll = to_clk_pll(hw);
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const struct pll_freq_tbl *f;
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bool enabled;
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u32 mode;
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u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N;
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f = find_freq(pll->freq_tbl, rate);
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if (!f)
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return -EINVAL;
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regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
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enabled = (mode & enable_mask) == enable_mask;
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if (enabled)
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clk_pll_disable(hw);
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regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);
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regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);
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regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);
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regmap_write(pll->clkr.regmap, pll->config_reg, f->ibits);
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if (enabled)
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clk_pll_enable(hw);
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return 0;
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}
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const struct clk_ops clk_pll_ops = {
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.enable = clk_pll_enable,
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.disable = clk_pll_disable,
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.recalc_rate = clk_pll_recalc_rate,
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.determine_rate = clk_pll_determine_rate,
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.set_rate = clk_pll_set_rate,
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};
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EXPORT_SYMBOL_GPL(clk_pll_ops);
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static int wait_for_pll(struct clk_pll *pll)
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{
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u32 val;
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int count;
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int ret;
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const char *name = clk_hw_get_name(&pll->clkr.hw);
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/* Wait for pll to enable. */
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for (count = 200; count > 0; count--) {
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ret = regmap_read(pll->clkr.regmap, pll->status_reg, &val);
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if (ret)
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return ret;
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if (val & BIT(pll->status_bit))
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return 0;
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udelay(1);
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}
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WARN(1, "%s didn't enable after voting for it!\n", name);
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return -ETIMEDOUT;
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}
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static int clk_pll_vote_enable(struct clk_hw *hw)
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{
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int ret;
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struct clk_pll *p = to_clk_pll(clk_hw_get_parent(hw));
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ret = clk_enable_regmap(hw);
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if (ret)
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return ret;
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return wait_for_pll(p);
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}
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const struct clk_ops clk_pll_vote_ops = {
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.enable = clk_pll_vote_enable,
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.disable = clk_disable_regmap,
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};
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EXPORT_SYMBOL_GPL(clk_pll_vote_ops);
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static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap,
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const struct pll_config *config)
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{
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u32 val;
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u32 mask;
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regmap_write(regmap, pll->l_reg, config->l);
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regmap_write(regmap, pll->m_reg, config->m);
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regmap_write(regmap, pll->n_reg, config->n);
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val = config->vco_val;
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val |= config->pre_div_val;
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val |= config->post_div_val;
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val |= config->mn_ena_mask;
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val |= config->main_output_mask;
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val |= config->aux_output_mask;
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mask = config->vco_mask;
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mask |= config->pre_div_mask;
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mask |= config->post_div_mask;
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mask |= config->mn_ena_mask;
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mask |= config->main_output_mask;
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mask |= config->aux_output_mask;
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regmap_update_bits(regmap, pll->config_reg, mask, val);
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}
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void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
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const struct pll_config *config, bool fsm_mode)
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{
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clk_pll_configure(pll, regmap, config);
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if (fsm_mode)
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qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 8);
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}
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EXPORT_SYMBOL_GPL(clk_pll_configure_sr);
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void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
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const struct pll_config *config, bool fsm_mode)
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{
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clk_pll_configure(pll, regmap, config);
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if (fsm_mode)
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qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 0);
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}
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EXPORT_SYMBOL_GPL(clk_pll_configure_sr_hpm_lp);
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static int clk_pll_sr2_enable(struct clk_hw *hw)
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{
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struct clk_pll *pll = to_clk_pll(hw);
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int ret;
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u32 mode;
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ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
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if (ret)
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return ret;
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/* Disable PLL bypass mode. */
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ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,
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PLL_BYPASSNL);
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if (ret)
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return ret;
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/*
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* H/W requires a 5us delay between disabling the bypass and
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* de-asserting the reset. Delay 10us just to be safe.
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*/
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udelay(10);
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/* De-assert active-low PLL reset. */
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ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,
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PLL_RESET_N);
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if (ret)
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return ret;
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ret = wait_for_pll(pll);
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if (ret)
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return ret;
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/* Enable PLL output. */
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return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,
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PLL_OUTCTRL);
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}
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static int
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clk_pll_sr2_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate)
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{
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struct clk_pll *pll = to_clk_pll(hw);
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const struct pll_freq_tbl *f;
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bool enabled;
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u32 mode;
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u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N;
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f = find_freq(pll->freq_tbl, rate);
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if (!f)
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return -EINVAL;
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regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
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enabled = (mode & enable_mask) == enable_mask;
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if (enabled)
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clk_pll_disable(hw);
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regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);
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regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);
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regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);
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if (enabled)
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clk_pll_sr2_enable(hw);
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return 0;
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}
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const struct clk_ops clk_pll_sr2_ops = {
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.enable = clk_pll_sr2_enable,
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.disable = clk_pll_disable,
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.set_rate = clk_pll_sr2_set_rate,
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.recalc_rate = clk_pll_recalc_rate,
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.determine_rate = clk_pll_determine_rate,
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};
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EXPORT_SYMBOL_GPL(clk_pll_sr2_ops);
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