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![Stephen Boyd](/assets/img/avatar_default.png)
* clk-renesas: (36 commits) clk: renesas: r7s9210: Add SPI clocks clk: renesas: r7s9210: Move table update to separate function clk: renesas: r7s9210: Convert some clocks to early clk: renesas: cpg-mssr: Add early clock support clk: renesas: r8a77970: Add TPU clock clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment dt-bindings: clock: renesas: cpg-mssr: Document r8a774c0 clk: renesas: cpg-mssr: Add r8a774c0 support clk: renesas: Add r8a774c0 CPG Core Clock Definitions clk: renesas: r8a7743: Add r8a7744 support clk: renesas: Add r8a7744 CPG Core Clock Definitions dt-bindings: clock: renesas: cpg-mssr: Document r8a7744 binding dt-bindings: clock: renesas: Convert to SPDX identifiers clk: renesas: cpg-mssr: Add R7S9210 support clk: renesas: r8a77970: Add TMU clocks clk: renesas: r8a77970: Add CMT clocks clk: renesas: r9a06g032: Fix UART34567 clock rate clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI clk: renesas: r8a77980: Add CMT clocks clk: renesas: r8a77990: Add missing I2C7 clock ...
1080 lines
25 KiB
C
1080 lines
25 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2015 Glider bvba
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*
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* Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
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*
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* Copyright (C) 2013 Ideas On Board SPRL
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* Copyright (C) 2015 Renesas Electronics Corp.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/renesas.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_clock.h>
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#include <linux/pm_domain.h>
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#include <linux/psci.h>
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#include <linux/reset-controller.h>
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#include <linux/slab.h>
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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#include "clk-div6.h"
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#ifdef DEBUG
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#define WARN_DEBUG(x) WARN_ON(x)
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#else
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#define WARN_DEBUG(x) do { } while (0)
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#endif
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/*
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* Module Standby and Software Reset register offets.
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*
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* If the registers exist, these are valid for SH-Mobile, R-Mobile,
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* R-Car Gen2, R-Car Gen3, and RZ/G1.
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* These are NOT valid for R-Car Gen1 and RZ/A1!
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*/
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/*
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* Module Stop Status Register offsets
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*/
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static const u16 mstpsr[] = {
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0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
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0x9A0, 0x9A4, 0x9A8, 0x9AC,
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};
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#define MSTPSR(i) mstpsr[i]
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/*
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* System Module Stop Control Register offsets
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*/
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static const u16 smstpcr[] = {
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0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
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0x990, 0x994, 0x998, 0x99C,
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};
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#define SMSTPCR(i) smstpcr[i]
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/*
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* Standby Control Register offsets (RZ/A)
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* Base address is FRQCR register
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*/
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static const u16 stbcr[] = {
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0xFFFF/*dummy*/, 0x010, 0x014, 0x410, 0x414, 0x418, 0x41C, 0x420,
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0x424, 0x428, 0x42C,
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};
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#define STBCR(i) stbcr[i]
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/*
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* Software Reset Register offsets
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*/
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static const u16 srcr[] = {
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0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,
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0x920, 0x924, 0x928, 0x92C,
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};
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#define SRCR(i) srcr[i]
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/* Realtime Module Stop Control Register offsets */
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#define RMSTPCR(i) (smstpcr[i] - 0x20)
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/* Modem Module Stop Control Register offsets (r8a73a4) */
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#define MMSTPCR(i) (smstpcr[i] + 0x20)
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/* Software Reset Clearing Register offsets */
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#define SRSTCLR(i) (0x940 + (i) * 4)
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/**
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* Clock Pulse Generator / Module Standby and Software Reset Private Data
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*
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* @rcdev: Optional reset controller entity
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* @dev: CPG/MSSR device
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* @base: CPG/MSSR register block base address
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* @rmw_lock: protects RMW register accesses
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* @clks: Array containing all Core and Module Clocks
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* @num_core_clks: Number of Core Clocks in clks[]
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* @num_mod_clks: Number of Module Clocks in clks[]
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* @last_dt_core_clk: ID of the last Core Clock exported to DT
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* @notifiers: Notifier chain to save/restore clock state for system resume
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* @smstpcr_saved[].mask: Mask of SMSTPCR[] bits under our control
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* @smstpcr_saved[].val: Saved values of SMSTPCR[]
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* @stbyctrl: This device has Standby Control Registers
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*/
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struct cpg_mssr_priv {
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#ifdef CONFIG_RESET_CONTROLLER
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struct reset_controller_dev rcdev;
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#endif
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struct device *dev;
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void __iomem *base;
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spinlock_t rmw_lock;
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struct device_node *np;
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struct clk **clks;
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unsigned int num_core_clks;
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unsigned int num_mod_clks;
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unsigned int last_dt_core_clk;
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bool stbyctrl;
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struct raw_notifier_head notifiers;
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struct {
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u32 mask;
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u32 val;
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} smstpcr_saved[ARRAY_SIZE(smstpcr)];
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};
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static struct cpg_mssr_priv *cpg_mssr_priv;
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/**
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* struct mstp_clock - MSTP gating clock
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* @hw: handle between common and hardware-specific interfaces
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* @index: MSTP clock number
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* @priv: CPG/MSSR private data
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*/
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struct mstp_clock {
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struct clk_hw hw;
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u32 index;
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struct cpg_mssr_priv *priv;
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};
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#define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
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static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
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{
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struct mstp_clock *clock = to_mstp_clock(hw);
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struct cpg_mssr_priv *priv = clock->priv;
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unsigned int reg = clock->index / 32;
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unsigned int bit = clock->index % 32;
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struct device *dev = priv->dev;
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u32 bitmask = BIT(bit);
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unsigned long flags;
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unsigned int i;
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u32 value;
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dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk,
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enable ? "ON" : "OFF");
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spin_lock_irqsave(&priv->rmw_lock, flags);
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if (priv->stbyctrl) {
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value = readb(priv->base + STBCR(reg));
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if (enable)
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value &= ~bitmask;
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else
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value |= bitmask;
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writeb(value, priv->base + STBCR(reg));
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/* dummy read to ensure write has completed */
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readb(priv->base + STBCR(reg));
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barrier_data(priv->base + STBCR(reg));
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} else {
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value = readl(priv->base + SMSTPCR(reg));
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if (enable)
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value &= ~bitmask;
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else
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value |= bitmask;
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writel(value, priv->base + SMSTPCR(reg));
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}
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spin_unlock_irqrestore(&priv->rmw_lock, flags);
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if (!enable || priv->stbyctrl)
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return 0;
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for (i = 1000; i > 0; --i) {
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if (!(readl(priv->base + MSTPSR(reg)) & bitmask))
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break;
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cpu_relax();
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}
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if (!i) {
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dev_err(dev, "Failed to enable SMSTP %p[%d]\n",
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priv->base + SMSTPCR(reg), bit);
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int cpg_mstp_clock_enable(struct clk_hw *hw)
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{
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return cpg_mstp_clock_endisable(hw, true);
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}
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static void cpg_mstp_clock_disable(struct clk_hw *hw)
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{
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cpg_mstp_clock_endisable(hw, false);
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}
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static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
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{
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struct mstp_clock *clock = to_mstp_clock(hw);
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struct cpg_mssr_priv *priv = clock->priv;
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u32 value;
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if (priv->stbyctrl)
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value = readb(priv->base + STBCR(clock->index / 32));
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else
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value = readl(priv->base + MSTPSR(clock->index / 32));
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return !(value & BIT(clock->index % 32));
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}
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static const struct clk_ops cpg_mstp_clock_ops = {
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.enable = cpg_mstp_clock_enable,
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.disable = cpg_mstp_clock_disable,
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.is_enabled = cpg_mstp_clock_is_enabled,
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};
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static
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struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
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void *data)
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{
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unsigned int clkidx = clkspec->args[1];
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struct cpg_mssr_priv *priv = data;
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struct device *dev = priv->dev;
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unsigned int idx;
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const char *type;
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struct clk *clk;
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int range_check;
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switch (clkspec->args[0]) {
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case CPG_CORE:
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type = "core";
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if (clkidx > priv->last_dt_core_clk) {
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dev_err(dev, "Invalid %s clock index %u\n", type,
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clkidx);
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return ERR_PTR(-EINVAL);
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}
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clk = priv->clks[clkidx];
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break;
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case CPG_MOD:
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type = "module";
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if (priv->stbyctrl) {
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idx = MOD_CLK_PACK_10(clkidx);
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range_check = 7 - (clkidx % 10);
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} else {
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idx = MOD_CLK_PACK(clkidx);
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range_check = 31 - (clkidx % 100);
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}
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if (range_check < 0 || idx >= priv->num_mod_clks) {
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dev_err(dev, "Invalid %s clock index %u\n", type,
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clkidx);
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return ERR_PTR(-EINVAL);
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}
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clk = priv->clks[priv->num_core_clks + idx];
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break;
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default:
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dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
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return ERR_PTR(-EINVAL);
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}
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if (IS_ERR(clk))
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dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
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PTR_ERR(clk));
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else
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dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
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clkspec->args[0], clkspec->args[1], clk,
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clk_get_rate(clk));
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return clk;
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}
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static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
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const struct cpg_mssr_info *info,
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struct cpg_mssr_priv *priv)
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{
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struct clk *clk = ERR_PTR(-ENOTSUPP), *parent;
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struct device *dev = priv->dev;
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unsigned int id = core->id, div = core->div;
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const char *parent_name;
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WARN_DEBUG(id >= priv->num_core_clks);
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WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
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if (!core->name) {
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/* Skip NULLified clock */
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return;
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}
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switch (core->type) {
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case CLK_TYPE_IN:
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clk = of_clk_get_by_name(priv->np, core->name);
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break;
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case CLK_TYPE_FF:
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case CLK_TYPE_DIV6P1:
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case CLK_TYPE_DIV6_RO:
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WARN_DEBUG(core->parent >= priv->num_core_clks);
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parent = priv->clks[core->parent];
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if (IS_ERR(parent)) {
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clk = parent;
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goto fail;
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}
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parent_name = __clk_get_name(parent);
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if (core->type == CLK_TYPE_DIV6_RO)
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/* Multiply with the DIV6 register value */
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div *= (readl(priv->base + core->offset) & 0x3f) + 1;
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if (core->type == CLK_TYPE_DIV6P1) {
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clk = cpg_div6_register(core->name, 1, &parent_name,
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priv->base + core->offset,
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&priv->notifiers);
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} else {
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clk = clk_register_fixed_factor(NULL, core->name,
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parent_name, 0,
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core->mult, div);
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}
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break;
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case CLK_TYPE_FR:
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clk = clk_register_fixed_rate(NULL, core->name, NULL, 0,
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core->mult);
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break;
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default:
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if (info->cpg_clk_register)
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clk = info->cpg_clk_register(dev, core, info,
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priv->clks, priv->base,
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&priv->notifiers);
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else
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dev_err(dev, "%s has unsupported core clock type %u\n",
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core->name, core->type);
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break;
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}
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if (IS_ERR_OR_NULL(clk))
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goto fail;
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dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
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priv->clks[id] = clk;
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return;
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fail:
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dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",
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core->name, PTR_ERR(clk));
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}
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static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
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const struct cpg_mssr_info *info,
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struct cpg_mssr_priv *priv)
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{
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struct mstp_clock *clock = NULL;
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struct device *dev = priv->dev;
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unsigned int id = mod->id;
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struct clk_init_data init;
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struct clk *parent, *clk;
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const char *parent_name;
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unsigned int i;
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WARN_DEBUG(id < priv->num_core_clks);
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WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
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WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
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WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
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if (!mod->name) {
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/* Skip NULLified clock */
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return;
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}
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parent = priv->clks[mod->parent];
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if (IS_ERR(parent)) {
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clk = parent;
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goto fail;
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}
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clock = kzalloc(sizeof(*clock), GFP_KERNEL);
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if (!clock) {
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clk = ERR_PTR(-ENOMEM);
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goto fail;
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}
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init.name = mod->name;
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init.ops = &cpg_mstp_clock_ops;
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init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
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for (i = 0; i < info->num_crit_mod_clks; i++)
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if (id == info->crit_mod_clks[i]) {
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dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n",
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mod->name);
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init.flags |= CLK_IS_CRITICAL;
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break;
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}
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parent_name = __clk_get_name(parent);
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init.parent_names = &parent_name;
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init.num_parents = 1;
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clock->index = id - priv->num_core_clks;
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clock->priv = priv;
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clock->hw.init = &init;
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clk = clk_register(NULL, &clock->hw);
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if (IS_ERR(clk))
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goto fail;
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dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
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priv->clks[id] = clk;
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priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32);
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return;
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fail:
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dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
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mod->name, PTR_ERR(clk));
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kfree(clock);
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}
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struct cpg_mssr_clk_domain {
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struct generic_pm_domain genpd;
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struct device_node *np;
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unsigned int num_core_pm_clks;
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unsigned int core_pm_clks[0];
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};
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static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain;
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static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec,
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struct cpg_mssr_clk_domain *pd)
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{
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unsigned int i;
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if (clkspec->np != pd->np || clkspec->args_count != 2)
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return false;
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switch (clkspec->args[0]) {
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case CPG_CORE:
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for (i = 0; i < pd->num_core_pm_clks; i++)
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if (clkspec->args[1] == pd->core_pm_clks[i])
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return true;
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return false;
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case CPG_MOD:
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return true;
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default:
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return false;
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}
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}
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int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev)
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{
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struct cpg_mssr_clk_domain *pd = cpg_mssr_clk_domain;
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struct device_node *np = dev->of_node;
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|
struct of_phandle_args clkspec;
|
|
struct clk *clk;
|
|
int i = 0;
|
|
int error;
|
|
|
|
if (!pd) {
|
|
dev_dbg(dev, "CPG/MSSR clock domain not yet available\n");
|
|
return -EPROBE_DEFER;
|
|
}
|
|
|
|
while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
|
|
&clkspec)) {
|
|
if (cpg_mssr_is_pm_clk(&clkspec, pd))
|
|
goto found;
|
|
|
|
of_node_put(clkspec.np);
|
|
i++;
|
|
}
|
|
|
|
return 0;
|
|
|
|
found:
|
|
clk = of_clk_get_from_provider(&clkspec);
|
|
of_node_put(clkspec.np);
|
|
|
|
if (IS_ERR(clk))
|
|
return PTR_ERR(clk);
|
|
|
|
error = pm_clk_create(dev);
|
|
if (error) {
|
|
dev_err(dev, "pm_clk_create failed %d\n", error);
|
|
goto fail_put;
|
|
}
|
|
|
|
error = pm_clk_add_clk(dev, clk);
|
|
if (error) {
|
|
dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error);
|
|
goto fail_destroy;
|
|
}
|
|
|
|
return 0;
|
|
|
|
fail_destroy:
|
|
pm_clk_destroy(dev);
|
|
fail_put:
|
|
clk_put(clk);
|
|
return error;
|
|
}
|
|
|
|
void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev)
|
|
{
|
|
if (!pm_clk_no_clocks(dev))
|
|
pm_clk_destroy(dev);
|
|
}
|
|
|
|
static int __init cpg_mssr_add_clk_domain(struct device *dev,
|
|
const unsigned int *core_pm_clks,
|
|
unsigned int num_core_pm_clks)
|
|
{
|
|
struct device_node *np = dev->of_node;
|
|
struct generic_pm_domain *genpd;
|
|
struct cpg_mssr_clk_domain *pd;
|
|
size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]);
|
|
|
|
pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL);
|
|
if (!pd)
|
|
return -ENOMEM;
|
|
|
|
pd->np = np;
|
|
pd->num_core_pm_clks = num_core_pm_clks;
|
|
memcpy(pd->core_pm_clks, core_pm_clks, pm_size);
|
|
|
|
genpd = &pd->genpd;
|
|
genpd->name = np->name;
|
|
genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
|
|
genpd->attach_dev = cpg_mssr_attach_dev;
|
|
genpd->detach_dev = cpg_mssr_detach_dev;
|
|
pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
|
|
cpg_mssr_clk_domain = pd;
|
|
|
|
of_genpd_add_provider_simple(np, genpd);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_RESET_CONTROLLER
|
|
|
|
#define rcdev_to_priv(x) container_of(x, struct cpg_mssr_priv, rcdev)
|
|
|
|
static int cpg_mssr_reset(struct reset_controller_dev *rcdev,
|
|
unsigned long id)
|
|
{
|
|
struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
|
|
unsigned int reg = id / 32;
|
|
unsigned int bit = id % 32;
|
|
u32 bitmask = BIT(bit);
|
|
unsigned long flags;
|
|
u32 value;
|
|
|
|
dev_dbg(priv->dev, "reset %u%02u\n", reg, bit);
|
|
|
|
/* Reset module */
|
|
spin_lock_irqsave(&priv->rmw_lock, flags);
|
|
value = readl(priv->base + SRCR(reg));
|
|
value |= bitmask;
|
|
writel(value, priv->base + SRCR(reg));
|
|
spin_unlock_irqrestore(&priv->rmw_lock, flags);
|
|
|
|
/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
|
|
udelay(35);
|
|
|
|
/* Release module from reset state */
|
|
writel(bitmask, priv->base + SRSTCLR(reg));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id)
|
|
{
|
|
struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
|
|
unsigned int reg = id / 32;
|
|
unsigned int bit = id % 32;
|
|
u32 bitmask = BIT(bit);
|
|
unsigned long flags;
|
|
u32 value;
|
|
|
|
dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);
|
|
|
|
spin_lock_irqsave(&priv->rmw_lock, flags);
|
|
value = readl(priv->base + SRCR(reg));
|
|
value |= bitmask;
|
|
writel(value, priv->base + SRCR(reg));
|
|
spin_unlock_irqrestore(&priv->rmw_lock, flags);
|
|
return 0;
|
|
}
|
|
|
|
static int cpg_mssr_deassert(struct reset_controller_dev *rcdev,
|
|
unsigned long id)
|
|
{
|
|
struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
|
|
unsigned int reg = id / 32;
|
|
unsigned int bit = id % 32;
|
|
u32 bitmask = BIT(bit);
|
|
|
|
dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit);
|
|
|
|
writel(bitmask, priv->base + SRSTCLR(reg));
|
|
return 0;
|
|
}
|
|
|
|
static int cpg_mssr_status(struct reset_controller_dev *rcdev,
|
|
unsigned long id)
|
|
{
|
|
struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
|
|
unsigned int reg = id / 32;
|
|
unsigned int bit = id % 32;
|
|
u32 bitmask = BIT(bit);
|
|
|
|
return !!(readl(priv->base + SRCR(reg)) & bitmask);
|
|
}
|
|
|
|
static const struct reset_control_ops cpg_mssr_reset_ops = {
|
|
.reset = cpg_mssr_reset,
|
|
.assert = cpg_mssr_assert,
|
|
.deassert = cpg_mssr_deassert,
|
|
.status = cpg_mssr_status,
|
|
};
|
|
|
|
static int cpg_mssr_reset_xlate(struct reset_controller_dev *rcdev,
|
|
const struct of_phandle_args *reset_spec)
|
|
{
|
|
struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
|
|
unsigned int unpacked = reset_spec->args[0];
|
|
unsigned int idx = MOD_CLK_PACK(unpacked);
|
|
|
|
if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) {
|
|
dev_err(priv->dev, "Invalid reset index %u\n", unpacked);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return idx;
|
|
}
|
|
|
|
static int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
|
|
{
|
|
priv->rcdev.ops = &cpg_mssr_reset_ops;
|
|
priv->rcdev.of_node = priv->dev->of_node;
|
|
priv->rcdev.of_reset_n_cells = 1;
|
|
priv->rcdev.of_xlate = cpg_mssr_reset_xlate;
|
|
priv->rcdev.nr_resets = priv->num_mod_clks;
|
|
return devm_reset_controller_register(priv->dev, &priv->rcdev);
|
|
}
|
|
|
|
#else /* !CONFIG_RESET_CONTROLLER */
|
|
static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif /* !CONFIG_RESET_CONTROLLER */
|
|
|
|
|
|
static const struct of_device_id cpg_mssr_match[] = {
|
|
#ifdef CONFIG_CLK_R7S9210
|
|
{
|
|
.compatible = "renesas,r7s9210-cpg-mssr",
|
|
.data = &r7s9210_cpg_mssr_info,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CLK_R8A7743
|
|
{
|
|
.compatible = "renesas,r8a7743-cpg-mssr",
|
|
.data = &r8a7743_cpg_mssr_info,
|
|
},
|
|
/* RZ/G1N is (almost) identical to RZ/G1M w.r.t. clocks. */
|
|
{
|
|
.compatible = "renesas,r8a7744-cpg-mssr",
|
|
.data = &r8a7743_cpg_mssr_info,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CLK_R8A7745
|
|
{
|
|
.compatible = "renesas,r8a7745-cpg-mssr",
|
|
.data = &r8a7745_cpg_mssr_info,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CLK_R8A77470
|
|
{
|
|
.compatible = "renesas,r8a77470-cpg-mssr",
|
|
.data = &r8a77470_cpg_mssr_info,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CLK_R8A774A1
|
|
{
|
|
.compatible = "renesas,r8a774a1-cpg-mssr",
|
|
.data = &r8a774a1_cpg_mssr_info,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CLK_R8A774C0
|
|
{
|
|
.compatible = "renesas,r8a774c0-cpg-mssr",
|
|
.data = &r8a774c0_cpg_mssr_info,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CLK_R8A7790
|
|
{
|
|
.compatible = "renesas,r8a7790-cpg-mssr",
|
|
.data = &r8a7790_cpg_mssr_info,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CLK_R8A7791
|
|
{
|
|
.compatible = "renesas,r8a7791-cpg-mssr",
|
|
.data = &r8a7791_cpg_mssr_info,
|
|
},
|
|
/* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */
|
|
{
|
|
.compatible = "renesas,r8a7793-cpg-mssr",
|
|
.data = &r8a7791_cpg_mssr_info,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CLK_R8A7792
|
|
{
|
|
.compatible = "renesas,r8a7792-cpg-mssr",
|
|
.data = &r8a7792_cpg_mssr_info,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CLK_R8A7794
|
|
{
|
|
.compatible = "renesas,r8a7794-cpg-mssr",
|
|
.data = &r8a7794_cpg_mssr_info,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CLK_R8A7795
|
|
{
|
|
.compatible = "renesas,r8a7795-cpg-mssr",
|
|
.data = &r8a7795_cpg_mssr_info,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CLK_R8A7796
|
|
{
|
|
.compatible = "renesas,r8a7796-cpg-mssr",
|
|
.data = &r8a7796_cpg_mssr_info,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CLK_R8A77965
|
|
{
|
|
.compatible = "renesas,r8a77965-cpg-mssr",
|
|
.data = &r8a77965_cpg_mssr_info,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CLK_R8A77970
|
|
{
|
|
.compatible = "renesas,r8a77970-cpg-mssr",
|
|
.data = &r8a77970_cpg_mssr_info,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CLK_R8A77980
|
|
{
|
|
.compatible = "renesas,r8a77980-cpg-mssr",
|
|
.data = &r8a77980_cpg_mssr_info,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CLK_R8A77990
|
|
{
|
|
.compatible = "renesas,r8a77990-cpg-mssr",
|
|
.data = &r8a77990_cpg_mssr_info,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CLK_R8A77995
|
|
{
|
|
.compatible = "renesas,r8a77995-cpg-mssr",
|
|
.data = &r8a77995_cpg_mssr_info,
|
|
},
|
|
#endif
|
|
{ /* sentinel */ }
|
|
};
|
|
|
|
static void cpg_mssr_del_clk_provider(void *data)
|
|
{
|
|
of_clk_del_provider(data);
|
|
}
|
|
|
|
#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
|
|
static int cpg_mssr_suspend_noirq(struct device *dev)
|
|
{
|
|
struct cpg_mssr_priv *priv = dev_get_drvdata(dev);
|
|
unsigned int reg;
|
|
|
|
/* This is the best we can do to check for the presence of PSCI */
|
|
if (!psci_ops.cpu_suspend)
|
|
return 0;
|
|
|
|
/* Save module registers with bits under our control */
|
|
for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
|
|
if (priv->smstpcr_saved[reg].mask)
|
|
priv->smstpcr_saved[reg].val =
|
|
readl(priv->base + SMSTPCR(reg));
|
|
}
|
|
|
|
/* Save core clocks */
|
|
raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cpg_mssr_resume_noirq(struct device *dev)
|
|
{
|
|
struct cpg_mssr_priv *priv = dev_get_drvdata(dev);
|
|
unsigned int reg, i;
|
|
u32 mask, oldval, newval;
|
|
|
|
/* This is the best we can do to check for the presence of PSCI */
|
|
if (!psci_ops.cpu_suspend)
|
|
return 0;
|
|
|
|
/* Restore core clocks */
|
|
raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL);
|
|
|
|
/* Restore module clocks */
|
|
for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
|
|
mask = priv->smstpcr_saved[reg].mask;
|
|
if (!mask)
|
|
continue;
|
|
|
|
if (priv->stbyctrl)
|
|
oldval = readb(priv->base + STBCR(reg));
|
|
else
|
|
oldval = readl(priv->base + SMSTPCR(reg));
|
|
newval = oldval & ~mask;
|
|
newval |= priv->smstpcr_saved[reg].val & mask;
|
|
if (newval == oldval)
|
|
continue;
|
|
|
|
if (priv->stbyctrl) {
|
|
writeb(newval, priv->base + STBCR(reg));
|
|
/* dummy read to ensure write has completed */
|
|
readb(priv->base + STBCR(reg));
|
|
barrier_data(priv->base + STBCR(reg));
|
|
continue;
|
|
} else
|
|
writel(newval, priv->base + SMSTPCR(reg));
|
|
|
|
/* Wait until enabled clocks are really enabled */
|
|
mask &= ~priv->smstpcr_saved[reg].val;
|
|
if (!mask)
|
|
continue;
|
|
|
|
for (i = 1000; i > 0; --i) {
|
|
oldval = readl(priv->base + MSTPSR(reg));
|
|
if (!(oldval & mask))
|
|
break;
|
|
cpu_relax();
|
|
}
|
|
|
|
if (!i)
|
|
dev_warn(dev, "Failed to enable SMSTP %p[0x%x]\n",
|
|
priv->base + SMSTPCR(reg), oldval & mask);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops cpg_mssr_pm = {
|
|
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cpg_mssr_suspend_noirq,
|
|
cpg_mssr_resume_noirq)
|
|
};
|
|
#define DEV_PM_OPS &cpg_mssr_pm
|
|
#else
|
|
#define DEV_PM_OPS NULL
|
|
#endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
|
|
|
|
static int __init cpg_mssr_common_init(struct device *dev,
|
|
struct device_node *np,
|
|
const struct cpg_mssr_info *info)
|
|
{
|
|
struct cpg_mssr_priv *priv;
|
|
struct clk **clks = NULL;
|
|
unsigned int nclks, i;
|
|
int error;
|
|
|
|
if (info->init) {
|
|
error = info->init(dev);
|
|
if (error)
|
|
return error;
|
|
}
|
|
|
|
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
priv->np = np;
|
|
priv->dev = dev;
|
|
spin_lock_init(&priv->rmw_lock);
|
|
|
|
priv->base = of_iomap(np, 0);
|
|
if (!priv->base) {
|
|
error = -ENOMEM;
|
|
goto out_err;
|
|
}
|
|
|
|
nclks = info->num_total_core_clks + info->num_hw_mod_clks;
|
|
clks = kmalloc_array(nclks, sizeof(*clks), GFP_KERNEL);
|
|
if (!clks) {
|
|
error = -ENOMEM;
|
|
goto out_err;
|
|
}
|
|
|
|
cpg_mssr_priv = priv;
|
|
priv->clks = clks;
|
|
priv->num_core_clks = info->num_total_core_clks;
|
|
priv->num_mod_clks = info->num_hw_mod_clks;
|
|
priv->last_dt_core_clk = info->last_dt_core_clk;
|
|
RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);
|
|
priv->stbyctrl = info->stbyctrl;
|
|
|
|
for (i = 0; i < nclks; i++)
|
|
clks[i] = ERR_PTR(-ENOENT);
|
|
|
|
error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
|
|
if (error)
|
|
goto out_err;
|
|
|
|
return 0;
|
|
|
|
out_err:
|
|
kfree(clks);
|
|
if (priv->base)
|
|
iounmap(priv->base);
|
|
kfree(priv);
|
|
|
|
return error;
|
|
}
|
|
|
|
void __init cpg_mssr_early_init(struct device_node *np,
|
|
const struct cpg_mssr_info *info)
|
|
{
|
|
int error;
|
|
int i;
|
|
|
|
error = cpg_mssr_common_init(NULL, np, info);
|
|
if (error)
|
|
return;
|
|
|
|
for (i = 0; i < info->num_early_core_clks; i++)
|
|
cpg_mssr_register_core_clk(&info->early_core_clks[i], info,
|
|
cpg_mssr_priv);
|
|
|
|
for (i = 0; i < info->num_early_mod_clks; i++)
|
|
cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info,
|
|
cpg_mssr_priv);
|
|
|
|
}
|
|
|
|
static int __init cpg_mssr_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct device_node *np = dev->of_node;
|
|
const struct cpg_mssr_info *info;
|
|
struct cpg_mssr_priv *priv;
|
|
unsigned int i;
|
|
int error;
|
|
|
|
info = of_device_get_match_data(dev);
|
|
|
|
if (!cpg_mssr_priv) {
|
|
error = cpg_mssr_common_init(dev, dev->of_node, info);
|
|
if (error)
|
|
return error;
|
|
}
|
|
|
|
priv = cpg_mssr_priv;
|
|
priv->dev = dev;
|
|
dev_set_drvdata(dev, priv);
|
|
|
|
for (i = 0; i < info->num_core_clks; i++)
|
|
cpg_mssr_register_core_clk(&info->core_clks[i], info, priv);
|
|
|
|
for (i = 0; i < info->num_mod_clks; i++)
|
|
cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv);
|
|
|
|
error = devm_add_action_or_reset(dev,
|
|
cpg_mssr_del_clk_provider,
|
|
np);
|
|
if (error)
|
|
return error;
|
|
|
|
error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks,
|
|
info->num_core_pm_clks);
|
|
if (error)
|
|
return error;
|
|
|
|
/* Reset Controller not supported for Standby Control SoCs */
|
|
if (info->stbyctrl)
|
|
return 0;
|
|
|
|
error = cpg_mssr_reset_controller_register(priv);
|
|
if (error)
|
|
return error;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver cpg_mssr_driver = {
|
|
.driver = {
|
|
.name = "renesas-cpg-mssr",
|
|
.of_match_table = cpg_mssr_match,
|
|
.pm = DEV_PM_OPS,
|
|
},
|
|
};
|
|
|
|
static int __init cpg_mssr_init(void)
|
|
{
|
|
return platform_driver_probe(&cpg_mssr_driver, cpg_mssr_probe);
|
|
}
|
|
|
|
subsys_initcall(cpg_mssr_init);
|
|
|
|
void __init cpg_core_nullify_range(struct cpg_core_clk *core_clks,
|
|
unsigned int num_core_clks,
|
|
unsigned int first_clk,
|
|
unsigned int last_clk)
|
|
{
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < num_core_clks; i++)
|
|
if (core_clks[i].id >= first_clk &&
|
|
core_clks[i].id <= last_clk)
|
|
core_clks[i].name = NULL;
|
|
}
|
|
|
|
void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks,
|
|
unsigned int num_mod_clks,
|
|
const unsigned int *clks, unsigned int n)
|
|
{
|
|
unsigned int i, j;
|
|
|
|
for (i = 0, j = 0; i < num_mod_clks && j < n; i++)
|
|
if (mod_clks[i].id == clks[j]) {
|
|
mod_clks[i].name = NULL;
|
|
j++;
|
|
}
|
|
}
|
|
|
|
void __init mssr_mod_reparent(struct mssr_mod_clk *mod_clks,
|
|
unsigned int num_mod_clks,
|
|
const struct mssr_mod_reparent *clks,
|
|
unsigned int n)
|
|
{
|
|
unsigned int i, j;
|
|
|
|
for (i = 0, j = 0; i < num_mod_clks && j < n; i++)
|
|
if (mod_clks[i].id == clks[j].clk) {
|
|
mod_clks[i].parent = clks[j].parent;
|
|
j++;
|
|
}
|
|
}
|
|
|
|
MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");
|
|
MODULE_LICENSE("GPL v2");
|