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![Linus Torvalds](/assets/img/avatar_default.png)
Pull crypto updates from Herbert Xu: "API: - Remove VLA usage - Add cryptostat user-space interface - Add notifier for new crypto algorithms Algorithms: - Add OFB mode - Remove speck Drivers: - Remove x86/sha*-mb as they are buggy - Remove pcbc(aes) from x86/aesni - Improve performance of arm/ghash-ce by up to 85% - Implement CTS-CBC in arm64/aes-blk, faster by up to 50% - Remove PMULL based arm64/crc32 driver - Use PMULL in arm64/crct10dif - Add aes-ctr support in s5p-sss - Add caam/qi2 driver Others: - Pick better transform if one becomes available in crc-t10dif" * 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (124 commits) crypto: chelsio - Update ntx queue received from cxgb4 crypto: ccree - avoid implicit enum conversion crypto: caam - add SPDX license identifier to all files crypto: caam/qi - simplify CGR allocation, freeing crypto: mxs-dcp - make symbols 'sha1_null_hash' and 'sha256_null_hash' static crypto: arm64/aes-blk - ensure XTS mask is always loaded crypto: testmgr - fix sizeof() on COMP_BUF_SIZE crypto: chtls - remove set but not used variable 'csk' crypto: axis - fix platform_no_drv_owner.cocci warnings crypto: x86/aes-ni - fix build error following fpu template removal crypto: arm64/aes - fix handling sub-block CTS-CBC inputs crypto: caam/qi2 - avoid double export crypto: mxs-dcp - Fix AES issues crypto: mxs-dcp - Fix SHA null hashes and output length crypto: mxs-dcp - Implement sha import/export crypto: aegis/generic - fix for big endian systems crypto: morus/generic - fix for big endian systems crypto: lrw - fix rebase error after out of bounds fix crypto: cavium/nitrox - use pci_alloc_irq_vectors() while enabling MSI-X. crypto: cavium/nitrox - NITROX command queue changes. ...
268 lines
6.4 KiB
C
268 lines
6.4 KiB
C
/**
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* This file is part of the Chelsio T4/T5/T6 Ethernet driver for Linux.
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*
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* Copyright (C) 2011-2016 Chelsio Communications. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation.
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*
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* Written and Maintained by:
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* Manoj Malviya (manojmalviya@chelsio.com)
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* Atul Gupta (atul.gupta@chelsio.com)
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* Jitendra Lulla (jlulla@chelsio.com)
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* Yeshaswi M R Gowda (yeshaswi@chelsio.com)
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* Harsh Jain (harsh@chelsio.com)
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/skbuff.h>
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#include <crypto/aes.h>
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#include <crypto/hash.h>
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#include "t4_msg.h"
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#include "chcr_core.h"
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#include "cxgb4_uld.h"
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static LIST_HEAD(uld_ctx_list);
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static DEFINE_MUTEX(dev_mutex);
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static atomic_t dev_count;
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static struct uld_ctx *ctx_rr;
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typedef int (*chcr_handler_func)(struct chcr_dev *dev, unsigned char *input);
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static int cpl_fw6_pld_handler(struct chcr_dev *dev, unsigned char *input);
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static void *chcr_uld_add(const struct cxgb4_lld_info *lld);
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static int chcr_uld_state_change(void *handle, enum cxgb4_state state);
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static chcr_handler_func work_handlers[NUM_CPL_CMDS] = {
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[CPL_FW6_PLD] = cpl_fw6_pld_handler,
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};
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static struct cxgb4_uld_info chcr_uld_info = {
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.name = DRV_MODULE_NAME,
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.nrxq = MAX_ULD_QSETS,
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/* Max ntxq will be derived from fw config file*/
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.rxq_size = 1024,
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.add = chcr_uld_add,
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.state_change = chcr_uld_state_change,
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.rx_handler = chcr_uld_rx_handler,
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#ifdef CONFIG_CHELSIO_IPSEC_INLINE
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.tx_handler = chcr_uld_tx_handler,
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#endif /* CONFIG_CHELSIO_IPSEC_INLINE */
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};
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struct uld_ctx *assign_chcr_device(void)
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{
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struct uld_ctx *u_ctx = NULL;
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/*
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* When multiple devices are present in system select
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* device in round-robin fashion for crypto operations
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* Although One session must use the same device to
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* maintain request-response ordering.
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*/
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mutex_lock(&dev_mutex);
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if (!list_empty(&uld_ctx_list)) {
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u_ctx = ctx_rr;
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if (list_is_last(&ctx_rr->entry, &uld_ctx_list))
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ctx_rr = list_first_entry(&uld_ctx_list,
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struct uld_ctx,
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entry);
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else
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ctx_rr = list_next_entry(ctx_rr, entry);
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}
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mutex_unlock(&dev_mutex);
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return u_ctx;
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}
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static int chcr_dev_add(struct uld_ctx *u_ctx)
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{
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struct chcr_dev *dev;
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dev = kzalloc(sizeof(*dev), GFP_KERNEL);
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if (!dev)
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return -ENXIO;
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spin_lock_init(&dev->lock_chcr_dev);
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u_ctx->dev = dev;
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dev->u_ctx = u_ctx;
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atomic_inc(&dev_count);
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mutex_lock(&dev_mutex);
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list_add_tail(&u_ctx->entry, &uld_ctx_list);
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if (!ctx_rr)
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ctx_rr = u_ctx;
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mutex_unlock(&dev_mutex);
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return 0;
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}
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static int chcr_dev_remove(struct uld_ctx *u_ctx)
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{
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if (ctx_rr == u_ctx) {
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if (list_is_last(&ctx_rr->entry, &uld_ctx_list))
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ctx_rr = list_first_entry(&uld_ctx_list,
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struct uld_ctx,
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entry);
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else
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ctx_rr = list_next_entry(ctx_rr, entry);
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}
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list_del(&u_ctx->entry);
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if (list_empty(&uld_ctx_list))
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ctx_rr = NULL;
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kfree(u_ctx->dev);
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u_ctx->dev = NULL;
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atomic_dec(&dev_count);
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return 0;
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}
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static int cpl_fw6_pld_handler(struct chcr_dev *dev,
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unsigned char *input)
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{
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struct crypto_async_request *req;
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struct cpl_fw6_pld *fw6_pld;
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u32 ack_err_status = 0;
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int error_status = 0;
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struct adapter *adap = padap(dev);
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fw6_pld = (struct cpl_fw6_pld *)input;
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req = (struct crypto_async_request *)(uintptr_t)be64_to_cpu(
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fw6_pld->data[1]);
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ack_err_status =
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ntohl(*(__be32 *)((unsigned char *)&fw6_pld->data[0] + 4));
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if (ack_err_status) {
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if (CHK_MAC_ERR_BIT(ack_err_status) ||
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CHK_PAD_ERR_BIT(ack_err_status))
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error_status = -EBADMSG;
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atomic_inc(&adap->chcr_stats.error);
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}
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/* call completion callback with failure status */
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if (req) {
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error_status = chcr_handle_resp(req, input, error_status);
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} else {
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pr_err("Incorrect request address from the firmware\n");
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return -EFAULT;
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}
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return 0;
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}
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int chcr_send_wr(struct sk_buff *skb)
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{
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return cxgb4_crypto_send(skb->dev, skb);
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}
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static void *chcr_uld_add(const struct cxgb4_lld_info *lld)
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{
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struct uld_ctx *u_ctx;
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/* Create the device and add it in the device list */
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if (!(lld->ulp_crypto & ULP_CRYPTO_LOOKASIDE))
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return ERR_PTR(-EOPNOTSUPP);
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/* Create the device and add it in the device list */
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u_ctx = kzalloc(sizeof(*u_ctx), GFP_KERNEL);
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if (!u_ctx) {
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u_ctx = ERR_PTR(-ENOMEM);
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goto out;
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}
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u_ctx->lldi = *lld;
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#ifdef CONFIG_CHELSIO_IPSEC_INLINE
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if (lld->crypto & ULP_CRYPTO_IPSEC_INLINE)
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chcr_add_xfrmops(lld);
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#endif /* CONFIG_CHELSIO_IPSEC_INLINE */
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out:
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return u_ctx;
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}
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int chcr_uld_rx_handler(void *handle, const __be64 *rsp,
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const struct pkt_gl *pgl)
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{
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struct uld_ctx *u_ctx = (struct uld_ctx *)handle;
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struct chcr_dev *dev = u_ctx->dev;
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const struct cpl_fw6_pld *rpl = (struct cpl_fw6_pld *)rsp;
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if (rpl->opcode != CPL_FW6_PLD) {
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pr_err("Unsupported opcode\n");
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return 0;
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}
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if (!pgl)
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work_handlers[rpl->opcode](dev, (unsigned char *)&rsp[1]);
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else
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work_handlers[rpl->opcode](dev, pgl->va);
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return 0;
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}
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#ifdef CONFIG_CHELSIO_IPSEC_INLINE
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int chcr_uld_tx_handler(struct sk_buff *skb, struct net_device *dev)
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{
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return chcr_ipsec_xmit(skb, dev);
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}
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#endif /* CONFIG_CHELSIO_IPSEC_INLINE */
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static int chcr_uld_state_change(void *handle, enum cxgb4_state state)
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{
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struct uld_ctx *u_ctx = handle;
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int ret = 0;
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switch (state) {
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case CXGB4_STATE_UP:
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if (!u_ctx->dev) {
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ret = chcr_dev_add(u_ctx);
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if (ret != 0)
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return ret;
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}
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if (atomic_read(&dev_count) == 1)
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ret = start_crypto();
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break;
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case CXGB4_STATE_DETACH:
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if (u_ctx->dev) {
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mutex_lock(&dev_mutex);
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chcr_dev_remove(u_ctx);
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mutex_unlock(&dev_mutex);
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}
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if (!atomic_read(&dev_count))
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stop_crypto();
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break;
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case CXGB4_STATE_START_RECOVERY:
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case CXGB4_STATE_DOWN:
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default:
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break;
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}
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return ret;
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}
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static int __init chcr_crypto_init(void)
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{
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cxgb4_register_uld(CXGB4_ULD_CRYPTO, &chcr_uld_info);
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return 0;
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}
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static void __exit chcr_crypto_exit(void)
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{
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struct uld_ctx *u_ctx, *tmp;
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if (atomic_read(&dev_count))
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stop_crypto();
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/* Remove all devices from list */
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mutex_lock(&dev_mutex);
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list_for_each_entry_safe(u_ctx, tmp, &uld_ctx_list, entry) {
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if (u_ctx->dev)
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chcr_dev_remove(u_ctx);
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kfree(u_ctx);
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}
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mutex_unlock(&dev_mutex);
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cxgb4_unregister_uld(CXGB4_ULD_CRYPTO);
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}
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module_init(chcr_crypto_init);
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module_exit(chcr_crypto_exit);
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MODULE_DESCRIPTION("Crypto Co-processor for Chelsio Terminator cards.");
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Chelsio Communications");
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MODULE_VERSION(DRV_VERSION);
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