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![Fabio Estevam](/assets/img/avatar_default.png)
mx8dv never entered into production and there is no other place in the kernel referring to this SoC, so remove it from the driver's compatible entry. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
693 lines
16 KiB
C
693 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* This is i.MX low power i2c controller driver.
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*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*/
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/i2c.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#define DRIVER_NAME "imx-lpi2c"
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#define LPI2C_PARAM 0x04 /* i2c RX/TX FIFO size */
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#define LPI2C_MCR 0x10 /* i2c contrl register */
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#define LPI2C_MSR 0x14 /* i2c status register */
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#define LPI2C_MIER 0x18 /* i2c interrupt enable */
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#define LPI2C_MCFGR0 0x20 /* i2c master configuration */
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#define LPI2C_MCFGR1 0x24 /* i2c master configuration */
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#define LPI2C_MCFGR2 0x28 /* i2c master configuration */
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#define LPI2C_MCFGR3 0x2C /* i2c master configuration */
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#define LPI2C_MCCR0 0x48 /* i2c master clk configuration */
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#define LPI2C_MCCR1 0x50 /* i2c master clk configuration */
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#define LPI2C_MFCR 0x58 /* i2c master FIFO control */
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#define LPI2C_MFSR 0x5C /* i2c master FIFO status */
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#define LPI2C_MTDR 0x60 /* i2c master TX data register */
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#define LPI2C_MRDR 0x70 /* i2c master RX data register */
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/* i2c command */
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#define TRAN_DATA 0X00
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#define RECV_DATA 0X01
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#define GEN_STOP 0X02
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#define RECV_DISCARD 0X03
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#define GEN_START 0X04
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#define START_NACK 0X05
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#define START_HIGH 0X06
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#define START_HIGH_NACK 0X07
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#define MCR_MEN BIT(0)
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#define MCR_RST BIT(1)
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#define MCR_DOZEN BIT(2)
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#define MCR_DBGEN BIT(3)
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#define MCR_RTF BIT(8)
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#define MCR_RRF BIT(9)
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#define MSR_TDF BIT(0)
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#define MSR_RDF BIT(1)
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#define MSR_SDF BIT(9)
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#define MSR_NDF BIT(10)
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#define MSR_ALF BIT(11)
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#define MSR_MBF BIT(24)
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#define MSR_BBF BIT(25)
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#define MIER_TDIE BIT(0)
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#define MIER_RDIE BIT(1)
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#define MIER_SDIE BIT(9)
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#define MIER_NDIE BIT(10)
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#define MCFGR1_AUTOSTOP BIT(8)
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#define MCFGR1_IGNACK BIT(9)
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#define MRDR_RXEMPTY BIT(14)
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#define I2C_CLK_RATIO 2
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#define CHUNK_DATA 256
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#define LPI2C_DEFAULT_RATE 100000
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#define STARDARD_MAX_BITRATE 400000
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#define FAST_MAX_BITRATE 1000000
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#define FAST_PLUS_MAX_BITRATE 3400000
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#define HIGHSPEED_MAX_BITRATE 5000000
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#define I2C_PM_TIMEOUT 10 /* ms */
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enum lpi2c_imx_mode {
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STANDARD, /* 100+Kbps */
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FAST, /* 400+Kbps */
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FAST_PLUS, /* 1.0+Mbps */
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HS, /* 3.4+Mbps */
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ULTRA_FAST, /* 5.0+Mbps */
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};
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enum lpi2c_imx_pincfg {
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TWO_PIN_OD,
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TWO_PIN_OO,
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TWO_PIN_PP,
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FOUR_PIN_PP,
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};
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struct lpi2c_imx_struct {
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struct i2c_adapter adapter;
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struct clk *clk;
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void __iomem *base;
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__u8 *rx_buf;
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__u8 *tx_buf;
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struct completion complete;
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unsigned int msglen;
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unsigned int delivered;
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unsigned int block_data;
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unsigned int bitrate;
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unsigned int txfifosize;
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unsigned int rxfifosize;
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enum lpi2c_imx_mode mode;
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};
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static void lpi2c_imx_intctrl(struct lpi2c_imx_struct *lpi2c_imx,
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unsigned int enable)
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{
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writel(enable, lpi2c_imx->base + LPI2C_MIER);
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}
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static int lpi2c_imx_bus_busy(struct lpi2c_imx_struct *lpi2c_imx)
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{
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unsigned long orig_jiffies = jiffies;
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unsigned int temp;
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while (1) {
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temp = readl(lpi2c_imx->base + LPI2C_MSR);
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/* check for arbitration lost, clear if set */
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if (temp & MSR_ALF) {
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writel(temp, lpi2c_imx->base + LPI2C_MSR);
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return -EAGAIN;
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}
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if (temp & (MSR_BBF | MSR_MBF))
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break;
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if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
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dev_dbg(&lpi2c_imx->adapter.dev, "bus not work\n");
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return -ETIMEDOUT;
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}
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schedule();
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}
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return 0;
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}
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static void lpi2c_imx_set_mode(struct lpi2c_imx_struct *lpi2c_imx)
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{
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unsigned int bitrate = lpi2c_imx->bitrate;
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enum lpi2c_imx_mode mode;
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if (bitrate < STARDARD_MAX_BITRATE)
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mode = STANDARD;
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else if (bitrate < FAST_MAX_BITRATE)
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mode = FAST;
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else if (bitrate < FAST_PLUS_MAX_BITRATE)
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mode = FAST_PLUS;
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else if (bitrate < HIGHSPEED_MAX_BITRATE)
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mode = HS;
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else
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mode = ULTRA_FAST;
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lpi2c_imx->mode = mode;
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}
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static int lpi2c_imx_start(struct lpi2c_imx_struct *lpi2c_imx,
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struct i2c_msg *msgs)
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{
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unsigned int temp;
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temp = readl(lpi2c_imx->base + LPI2C_MCR);
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temp |= MCR_RRF | MCR_RTF;
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writel(temp, lpi2c_imx->base + LPI2C_MCR);
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writel(0x7f00, lpi2c_imx->base + LPI2C_MSR);
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temp = i2c_8bit_addr_from_msg(msgs) | (GEN_START << 8);
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writel(temp, lpi2c_imx->base + LPI2C_MTDR);
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return lpi2c_imx_bus_busy(lpi2c_imx);
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}
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static void lpi2c_imx_stop(struct lpi2c_imx_struct *lpi2c_imx)
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{
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unsigned long orig_jiffies = jiffies;
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unsigned int temp;
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writel(GEN_STOP << 8, lpi2c_imx->base + LPI2C_MTDR);
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do {
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temp = readl(lpi2c_imx->base + LPI2C_MSR);
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if (temp & MSR_SDF)
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break;
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if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
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dev_dbg(&lpi2c_imx->adapter.dev, "stop timeout\n");
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break;
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}
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schedule();
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} while (1);
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}
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/* CLKLO = I2C_CLK_RATIO * CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI/2 */
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static int lpi2c_imx_config(struct lpi2c_imx_struct *lpi2c_imx)
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{
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u8 prescale, filt, sethold, clkhi, clklo, datavd;
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unsigned int clk_rate, clk_cycle;
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enum lpi2c_imx_pincfg pincfg;
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unsigned int temp;
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lpi2c_imx_set_mode(lpi2c_imx);
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clk_rate = clk_get_rate(lpi2c_imx->clk);
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if (lpi2c_imx->mode == HS || lpi2c_imx->mode == ULTRA_FAST)
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filt = 0;
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else
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filt = 2;
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for (prescale = 0; prescale <= 7; prescale++) {
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clk_cycle = clk_rate / ((1 << prescale) * lpi2c_imx->bitrate)
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- 3 - (filt >> 1);
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clkhi = (clk_cycle + I2C_CLK_RATIO) / (I2C_CLK_RATIO + 1);
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clklo = clk_cycle - clkhi;
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if (clklo < 64)
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break;
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}
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if (prescale > 7)
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return -EINVAL;
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/* set MCFGR1: PINCFG, PRESCALE, IGNACK */
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if (lpi2c_imx->mode == ULTRA_FAST)
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pincfg = TWO_PIN_OO;
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else
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pincfg = TWO_PIN_OD;
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temp = prescale | pincfg << 24;
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if (lpi2c_imx->mode == ULTRA_FAST)
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temp |= MCFGR1_IGNACK;
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writel(temp, lpi2c_imx->base + LPI2C_MCFGR1);
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/* set MCFGR2: FILTSDA, FILTSCL */
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temp = (filt << 16) | (filt << 24);
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writel(temp, lpi2c_imx->base + LPI2C_MCFGR2);
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/* set MCCR: DATAVD, SETHOLD, CLKHI, CLKLO */
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sethold = clkhi;
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datavd = clkhi >> 1;
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temp = datavd << 24 | sethold << 16 | clkhi << 8 | clklo;
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if (lpi2c_imx->mode == HS)
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writel(temp, lpi2c_imx->base + LPI2C_MCCR1);
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else
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writel(temp, lpi2c_imx->base + LPI2C_MCCR0);
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return 0;
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}
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static int lpi2c_imx_master_enable(struct lpi2c_imx_struct *lpi2c_imx)
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{
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unsigned int temp;
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int ret;
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ret = pm_runtime_get_sync(lpi2c_imx->adapter.dev.parent);
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if (ret < 0)
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return ret;
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temp = MCR_RST;
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writel(temp, lpi2c_imx->base + LPI2C_MCR);
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writel(0, lpi2c_imx->base + LPI2C_MCR);
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ret = lpi2c_imx_config(lpi2c_imx);
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if (ret)
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goto rpm_put;
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temp = readl(lpi2c_imx->base + LPI2C_MCR);
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temp |= MCR_MEN;
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writel(temp, lpi2c_imx->base + LPI2C_MCR);
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return 0;
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rpm_put:
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pm_runtime_mark_last_busy(lpi2c_imx->adapter.dev.parent);
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pm_runtime_put_autosuspend(lpi2c_imx->adapter.dev.parent);
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return ret;
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}
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static int lpi2c_imx_master_disable(struct lpi2c_imx_struct *lpi2c_imx)
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{
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u32 temp;
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temp = readl(lpi2c_imx->base + LPI2C_MCR);
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temp &= ~MCR_MEN;
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writel(temp, lpi2c_imx->base + LPI2C_MCR);
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pm_runtime_mark_last_busy(lpi2c_imx->adapter.dev.parent);
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pm_runtime_put_autosuspend(lpi2c_imx->adapter.dev.parent);
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return 0;
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}
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static int lpi2c_imx_msg_complete(struct lpi2c_imx_struct *lpi2c_imx)
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{
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unsigned long timeout;
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timeout = wait_for_completion_timeout(&lpi2c_imx->complete, HZ);
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return timeout ? 0 : -ETIMEDOUT;
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}
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static int lpi2c_imx_txfifo_empty(struct lpi2c_imx_struct *lpi2c_imx)
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{
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unsigned long orig_jiffies = jiffies;
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u32 txcnt;
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do {
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txcnt = readl(lpi2c_imx->base + LPI2C_MFSR) & 0xff;
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if (readl(lpi2c_imx->base + LPI2C_MSR) & MSR_NDF) {
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dev_dbg(&lpi2c_imx->adapter.dev, "NDF detected\n");
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return -EIO;
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}
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if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
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dev_dbg(&lpi2c_imx->adapter.dev, "txfifo empty timeout\n");
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return -ETIMEDOUT;
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}
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schedule();
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} while (txcnt);
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return 0;
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}
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static void lpi2c_imx_set_tx_watermark(struct lpi2c_imx_struct *lpi2c_imx)
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{
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writel(lpi2c_imx->txfifosize >> 1, lpi2c_imx->base + LPI2C_MFCR);
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}
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static void lpi2c_imx_set_rx_watermark(struct lpi2c_imx_struct *lpi2c_imx)
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{
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unsigned int temp, remaining;
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remaining = lpi2c_imx->msglen - lpi2c_imx->delivered;
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if (remaining > (lpi2c_imx->rxfifosize >> 1))
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temp = lpi2c_imx->rxfifosize >> 1;
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else
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temp = 0;
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writel(temp << 16, lpi2c_imx->base + LPI2C_MFCR);
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}
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static void lpi2c_imx_write_txfifo(struct lpi2c_imx_struct *lpi2c_imx)
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{
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unsigned int data, txcnt;
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txcnt = readl(lpi2c_imx->base + LPI2C_MFSR) & 0xff;
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while (txcnt < lpi2c_imx->txfifosize) {
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if (lpi2c_imx->delivered == lpi2c_imx->msglen)
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break;
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data = lpi2c_imx->tx_buf[lpi2c_imx->delivered++];
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writel(data, lpi2c_imx->base + LPI2C_MTDR);
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txcnt++;
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}
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if (lpi2c_imx->delivered < lpi2c_imx->msglen)
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lpi2c_imx_intctrl(lpi2c_imx, MIER_TDIE | MIER_NDIE);
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else
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complete(&lpi2c_imx->complete);
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}
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static void lpi2c_imx_read_rxfifo(struct lpi2c_imx_struct *lpi2c_imx)
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{
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unsigned int blocklen, remaining;
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unsigned int temp, data;
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do {
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data = readl(lpi2c_imx->base + LPI2C_MRDR);
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if (data & MRDR_RXEMPTY)
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break;
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lpi2c_imx->rx_buf[lpi2c_imx->delivered++] = data & 0xff;
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} while (1);
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/*
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* First byte is the length of remaining packet in the SMBus block
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* data read. Add it to msgs->len.
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*/
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if (lpi2c_imx->block_data) {
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blocklen = lpi2c_imx->rx_buf[0];
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lpi2c_imx->msglen += blocklen;
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}
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remaining = lpi2c_imx->msglen - lpi2c_imx->delivered;
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if (!remaining) {
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complete(&lpi2c_imx->complete);
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return;
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}
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/* not finished, still waiting for rx data */
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lpi2c_imx_set_rx_watermark(lpi2c_imx);
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/* multiple receive commands */
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if (lpi2c_imx->block_data) {
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lpi2c_imx->block_data = 0;
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temp = remaining;
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temp |= (RECV_DATA << 8);
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writel(temp, lpi2c_imx->base + LPI2C_MTDR);
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} else if (!(lpi2c_imx->delivered & 0xff)) {
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temp = (remaining > CHUNK_DATA ? CHUNK_DATA : remaining) - 1;
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temp |= (RECV_DATA << 8);
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writel(temp, lpi2c_imx->base + LPI2C_MTDR);
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}
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lpi2c_imx_intctrl(lpi2c_imx, MIER_RDIE);
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}
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static void lpi2c_imx_write(struct lpi2c_imx_struct *lpi2c_imx,
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struct i2c_msg *msgs)
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{
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lpi2c_imx->tx_buf = msgs->buf;
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lpi2c_imx_set_tx_watermark(lpi2c_imx);
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lpi2c_imx_write_txfifo(lpi2c_imx);
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}
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static void lpi2c_imx_read(struct lpi2c_imx_struct *lpi2c_imx,
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struct i2c_msg *msgs)
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{
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unsigned int temp;
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lpi2c_imx->rx_buf = msgs->buf;
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lpi2c_imx->block_data = msgs->flags & I2C_M_RECV_LEN;
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lpi2c_imx_set_rx_watermark(lpi2c_imx);
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temp = msgs->len > CHUNK_DATA ? CHUNK_DATA - 1 : msgs->len - 1;
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temp |= (RECV_DATA << 8);
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writel(temp, lpi2c_imx->base + LPI2C_MTDR);
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lpi2c_imx_intctrl(lpi2c_imx, MIER_RDIE | MIER_NDIE);
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}
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static int lpi2c_imx_xfer(struct i2c_adapter *adapter,
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struct i2c_msg *msgs, int num)
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{
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struct lpi2c_imx_struct *lpi2c_imx = i2c_get_adapdata(adapter);
|
|
unsigned int temp;
|
|
int i, result;
|
|
|
|
result = lpi2c_imx_master_enable(lpi2c_imx);
|
|
if (result)
|
|
return result;
|
|
|
|
for (i = 0; i < num; i++) {
|
|
result = lpi2c_imx_start(lpi2c_imx, &msgs[i]);
|
|
if (result)
|
|
goto disable;
|
|
|
|
/* quick smbus */
|
|
if (num == 1 && msgs[0].len == 0)
|
|
goto stop;
|
|
|
|
lpi2c_imx->delivered = 0;
|
|
lpi2c_imx->msglen = msgs[i].len;
|
|
init_completion(&lpi2c_imx->complete);
|
|
|
|
if (msgs[i].flags & I2C_M_RD)
|
|
lpi2c_imx_read(lpi2c_imx, &msgs[i]);
|
|
else
|
|
lpi2c_imx_write(lpi2c_imx, &msgs[i]);
|
|
|
|
result = lpi2c_imx_msg_complete(lpi2c_imx);
|
|
if (result)
|
|
goto stop;
|
|
|
|
if (!(msgs[i].flags & I2C_M_RD)) {
|
|
result = lpi2c_imx_txfifo_empty(lpi2c_imx);
|
|
if (result)
|
|
goto stop;
|
|
}
|
|
}
|
|
|
|
stop:
|
|
lpi2c_imx_stop(lpi2c_imx);
|
|
|
|
temp = readl(lpi2c_imx->base + LPI2C_MSR);
|
|
if ((temp & MSR_NDF) && !result)
|
|
result = -EIO;
|
|
|
|
disable:
|
|
lpi2c_imx_master_disable(lpi2c_imx);
|
|
|
|
dev_dbg(&lpi2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
|
|
(result < 0) ? "error" : "success msg",
|
|
(result < 0) ? result : num);
|
|
|
|
return (result < 0) ? result : num;
|
|
}
|
|
|
|
static irqreturn_t lpi2c_imx_isr(int irq, void *dev_id)
|
|
{
|
|
struct lpi2c_imx_struct *lpi2c_imx = dev_id;
|
|
unsigned int temp;
|
|
|
|
lpi2c_imx_intctrl(lpi2c_imx, 0);
|
|
temp = readl(lpi2c_imx->base + LPI2C_MSR);
|
|
|
|
if (temp & MSR_RDF)
|
|
lpi2c_imx_read_rxfifo(lpi2c_imx);
|
|
|
|
if (temp & MSR_TDF)
|
|
lpi2c_imx_write_txfifo(lpi2c_imx);
|
|
|
|
if (temp & MSR_NDF)
|
|
complete(&lpi2c_imx->complete);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static u32 lpi2c_imx_func(struct i2c_adapter *adapter)
|
|
{
|
|
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
|
|
I2C_FUNC_SMBUS_READ_BLOCK_DATA;
|
|
}
|
|
|
|
static const struct i2c_algorithm lpi2c_imx_algo = {
|
|
.master_xfer = lpi2c_imx_xfer,
|
|
.functionality = lpi2c_imx_func,
|
|
};
|
|
|
|
static const struct of_device_id lpi2c_imx_of_match[] = {
|
|
{ .compatible = "fsl,imx7ulp-lpi2c" },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, lpi2c_imx_of_match);
|
|
|
|
static int lpi2c_imx_probe(struct platform_device *pdev)
|
|
{
|
|
struct lpi2c_imx_struct *lpi2c_imx;
|
|
struct resource *res;
|
|
unsigned int temp;
|
|
int irq, ret;
|
|
|
|
lpi2c_imx = devm_kzalloc(&pdev->dev, sizeof(*lpi2c_imx), GFP_KERNEL);
|
|
if (!lpi2c_imx)
|
|
return -ENOMEM;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
lpi2c_imx->base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(lpi2c_imx->base))
|
|
return PTR_ERR(lpi2c_imx->base);
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_err(&pdev->dev, "can't get irq number\n");
|
|
return irq;
|
|
}
|
|
|
|
lpi2c_imx->adapter.owner = THIS_MODULE;
|
|
lpi2c_imx->adapter.algo = &lpi2c_imx_algo;
|
|
lpi2c_imx->adapter.dev.parent = &pdev->dev;
|
|
lpi2c_imx->adapter.dev.of_node = pdev->dev.of_node;
|
|
strlcpy(lpi2c_imx->adapter.name, pdev->name,
|
|
sizeof(lpi2c_imx->adapter.name));
|
|
|
|
lpi2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(lpi2c_imx->clk)) {
|
|
dev_err(&pdev->dev, "can't get I2C peripheral clock\n");
|
|
return PTR_ERR(lpi2c_imx->clk);
|
|
}
|
|
|
|
ret = of_property_read_u32(pdev->dev.of_node,
|
|
"clock-frequency", &lpi2c_imx->bitrate);
|
|
if (ret)
|
|
lpi2c_imx->bitrate = LPI2C_DEFAULT_RATE;
|
|
|
|
ret = devm_request_irq(&pdev->dev, irq, lpi2c_imx_isr, 0,
|
|
pdev->name, lpi2c_imx);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "can't claim irq %d\n", irq);
|
|
return ret;
|
|
}
|
|
|
|
i2c_set_adapdata(&lpi2c_imx->adapter, lpi2c_imx);
|
|
platform_set_drvdata(pdev, lpi2c_imx);
|
|
|
|
ret = clk_prepare_enable(lpi2c_imx->clk);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "clk enable failed %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT);
|
|
pm_runtime_use_autosuspend(&pdev->dev);
|
|
pm_runtime_get_noresume(&pdev->dev);
|
|
pm_runtime_set_active(&pdev->dev);
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
temp = readl(lpi2c_imx->base + LPI2C_PARAM);
|
|
lpi2c_imx->txfifosize = 1 << (temp & 0x0f);
|
|
lpi2c_imx->rxfifosize = 1 << ((temp >> 8) & 0x0f);
|
|
|
|
ret = i2c_add_adapter(&lpi2c_imx->adapter);
|
|
if (ret)
|
|
goto rpm_disable;
|
|
|
|
pm_runtime_mark_last_busy(&pdev->dev);
|
|
pm_runtime_put_autosuspend(&pdev->dev);
|
|
|
|
dev_info(&lpi2c_imx->adapter.dev, "LPI2C adapter registered\n");
|
|
|
|
return 0;
|
|
|
|
rpm_disable:
|
|
pm_runtime_put(&pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
pm_runtime_dont_use_autosuspend(&pdev->dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int lpi2c_imx_remove(struct platform_device *pdev)
|
|
{
|
|
struct lpi2c_imx_struct *lpi2c_imx = platform_get_drvdata(pdev);
|
|
|
|
i2c_del_adapter(&lpi2c_imx->adapter);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
pm_runtime_dont_use_autosuspend(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int lpi2c_runtime_suspend(struct device *dev)
|
|
{
|
|
struct lpi2c_imx_struct *lpi2c_imx = dev_get_drvdata(dev);
|
|
|
|
clk_disable_unprepare(lpi2c_imx->clk);
|
|
pinctrl_pm_select_sleep_state(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int lpi2c_runtime_resume(struct device *dev)
|
|
{
|
|
struct lpi2c_imx_struct *lpi2c_imx = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
pinctrl_pm_select_default_state(dev);
|
|
ret = clk_prepare_enable(lpi2c_imx->clk);
|
|
if (ret) {
|
|
dev_err(dev, "failed to enable I2C clock, ret=%d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops lpi2c_pm_ops = {
|
|
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
|
pm_runtime_force_resume)
|
|
SET_RUNTIME_PM_OPS(lpi2c_runtime_suspend,
|
|
lpi2c_runtime_resume, NULL)
|
|
};
|
|
#define IMX_LPI2C_PM (&lpi2c_pm_ops)
|
|
#else
|
|
#define IMX_LPI2C_PM NULL
|
|
#endif
|
|
|
|
static struct platform_driver lpi2c_imx_driver = {
|
|
.probe = lpi2c_imx_probe,
|
|
.remove = lpi2c_imx_remove,
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
.of_match_table = lpi2c_imx_of_match,
|
|
.pm = IMX_LPI2C_PM,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(lpi2c_imx_driver);
|
|
|
|
MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>");
|
|
MODULE_DESCRIPTION("I2C adapter driver for LPI2C bus");
|
|
MODULE_LICENSE("GPL");
|