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![Douglas Anderson](/assets/img/avatar_default.png)
The -EPROBE_DEFER virus demands special case code to avoid printing error messages when the error is only -EPROBE_DEFER. Spread the virus to a new host: qusb2_phy_probe(). Specifically handle when our regulators might not be ready yet. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
893 lines
23 KiB
C
893 lines
23 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/nvmem-consumer.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#include <dt-bindings/phy/phy-qcom-qusb2.h>
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#define QUSB2PHY_PLL_TEST 0x04
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#define CLK_REF_SEL BIT(7)
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#define QUSB2PHY_PLL_TUNE 0x08
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#define QUSB2PHY_PLL_USER_CTL1 0x0c
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#define QUSB2PHY_PLL_USER_CTL2 0x10
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#define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c
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#define QUSB2PHY_PLL_PWR_CTRL 0x18
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/* QUSB2PHY_PLL_STATUS register bits */
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#define PLL_LOCKED BIT(5)
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/* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */
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#define CORE_READY_STATUS BIT(0)
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/* QUSB2PHY_PORT_POWERDOWN register bits */
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#define CLAMP_N_EN BIT(5)
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#define FREEZIO_N BIT(1)
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#define POWER_DOWN BIT(0)
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/* QUSB2PHY_PWR_CTRL1 register bits */
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#define PWR_CTRL1_VREF_SUPPLY_TRIM BIT(5)
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#define PWR_CTRL1_CLAMP_N_EN BIT(1)
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#define QUSB2PHY_REFCLK_ENABLE BIT(0)
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#define PHY_CLK_SCHEME_SEL BIT(0)
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/* QUSB2PHY_INTR_CTRL register bits */
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#define DMSE_INTR_HIGH_SEL BIT(4)
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#define DPSE_INTR_HIGH_SEL BIT(3)
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#define CHG_DET_INTR_EN BIT(2)
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#define DMSE_INTR_EN BIT(1)
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#define DPSE_INTR_EN BIT(0)
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/* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */
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#define CORE_PLL_EN_FROM_RESET BIT(4)
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#define CORE_RESET BIT(5)
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#define CORE_RESET_MUX BIT(6)
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/* QUSB2PHY_IMP_CTRL1 register bits */
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#define IMP_RES_OFFSET_MASK GENMASK(5, 0)
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#define IMP_RES_OFFSET_SHIFT 0x0
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/* QUSB2PHY_PORT_TUNE1 register bits */
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#define HSTX_TRIM_MASK GENMASK(7, 4)
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#define HSTX_TRIM_SHIFT 0x4
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#define PREEMPH_WIDTH_HALF_BIT BIT(2)
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#define PREEMPHASIS_EN_MASK GENMASK(1, 0)
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#define PREEMPHASIS_EN_SHIFT 0x0
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#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04
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#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c
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#define QUSB2PHY_PLL_CMODE 0x2c
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#define QUSB2PHY_PLL_LOCK_DELAY 0x184
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#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0xb4
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#define QUSB2PHY_PLL_BIAS_CONTROL_1 0x194
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#define QUSB2PHY_PLL_BIAS_CONTROL_2 0x198
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#define QUSB2PHY_PWR_CTRL2 0x214
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#define QUSB2PHY_IMP_CTRL1 0x220
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#define QUSB2PHY_IMP_CTRL2 0x224
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#define QUSB2PHY_CHG_CTRL2 0x23c
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struct qusb2_phy_init_tbl {
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unsigned int offset;
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unsigned int val;
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/*
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* register part of layout ?
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* if yes, then offset gives index in the reg-layout
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*/
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int in_layout;
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};
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#define QUSB2_PHY_INIT_CFG(o, v) \
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{ \
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.offset = o, \
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.val = v, \
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}
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#define QUSB2_PHY_INIT_CFG_L(o, v) \
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{ \
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.offset = o, \
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.val = v, \
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.in_layout = 1, \
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}
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/* set of registers with offsets different per-PHY */
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enum qusb2phy_reg_layout {
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QUSB2PHY_PLL_CORE_INPUT_OVERRIDE,
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QUSB2PHY_PLL_STATUS,
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QUSB2PHY_PORT_TUNE1,
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QUSB2PHY_PORT_TUNE2,
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QUSB2PHY_PORT_TUNE3,
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QUSB2PHY_PORT_TUNE4,
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QUSB2PHY_PORT_TUNE5,
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QUSB2PHY_PORT_TEST1,
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QUSB2PHY_PORT_TEST2,
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QUSB2PHY_PORT_POWERDOWN,
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QUSB2PHY_INTR_CTRL,
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};
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static const unsigned int msm8996_regs_layout[] = {
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[QUSB2PHY_PLL_STATUS] = 0x38,
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[QUSB2PHY_PORT_TUNE1] = 0x80,
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[QUSB2PHY_PORT_TUNE2] = 0x84,
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[QUSB2PHY_PORT_TUNE3] = 0x88,
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[QUSB2PHY_PORT_TUNE4] = 0x8c,
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[QUSB2PHY_PORT_TUNE5] = 0x90,
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[QUSB2PHY_PORT_TEST1] = 0xb8,
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[QUSB2PHY_PORT_TEST2] = 0x9c,
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[QUSB2PHY_PORT_POWERDOWN] = 0xb4,
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[QUSB2PHY_INTR_CTRL] = 0xbc,
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};
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static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
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};
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static const unsigned int sdm845_regs_layout[] = {
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[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8,
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[QUSB2PHY_PLL_STATUS] = 0x1a0,
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[QUSB2PHY_PORT_TUNE1] = 0x240,
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[QUSB2PHY_PORT_TUNE2] = 0x244,
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[QUSB2PHY_PORT_TUNE3] = 0x248,
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[QUSB2PHY_PORT_TUNE4] = 0x24c,
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[QUSB2PHY_PORT_TUNE5] = 0x250,
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[QUSB2PHY_PORT_TEST1] = 0x254,
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[QUSB2PHY_PORT_TEST2] = 0x258,
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[QUSB2PHY_PORT_POWERDOWN] = 0x210,
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[QUSB2PHY_INTR_CTRL] = 0x230,
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};
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static const struct qusb2_phy_init_tbl sdm845_init_tbl[] = {
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_1, 0x40),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_2, 0x20),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PWR_CTRL2, 0x21),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL1, 0x0),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL2, 0x58),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x30),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x29),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0xca),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x04),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x03),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_CHG_CTRL2, 0x0),
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};
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struct qusb2_phy_cfg {
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const struct qusb2_phy_init_tbl *tbl;
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/* number of entries in the table */
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unsigned int tbl_num;
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/* offset to PHY_CLK_SCHEME register in TCSR map */
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unsigned int clk_scheme_offset;
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/* array of registers with different offsets */
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const unsigned int *regs;
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unsigned int mask_core_ready;
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unsigned int disable_ctrl;
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unsigned int autoresume_en;
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/* true if PHY has PLL_TEST register to select clk_scheme */
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bool has_pll_test;
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/* true if TUNE1 register must be updated by fused value, else TUNE2 */
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bool update_tune1_with_efuse;
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/* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */
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bool has_pll_override;
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};
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static const struct qusb2_phy_cfg msm8996_phy_cfg = {
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.tbl = msm8996_init_tbl,
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.tbl_num = ARRAY_SIZE(msm8996_init_tbl),
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.regs = msm8996_regs_layout,
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.has_pll_test = true,
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.disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
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.mask_core_ready = PLL_LOCKED,
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.autoresume_en = BIT(3),
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};
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static const struct qusb2_phy_cfg sdm845_phy_cfg = {
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.tbl = sdm845_init_tbl,
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.tbl_num = ARRAY_SIZE(sdm845_init_tbl),
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.regs = sdm845_regs_layout,
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.disable_ctrl = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN |
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POWER_DOWN),
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.mask_core_ready = CORE_READY_STATUS,
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.has_pll_override = true,
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.autoresume_en = BIT(0),
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};
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static const char * const qusb2_phy_vreg_names[] = {
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"vdda-pll", "vdda-phy-dpdm",
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};
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#define QUSB2_NUM_VREGS ARRAY_SIZE(qusb2_phy_vreg_names)
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/**
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* struct qusb2_phy - structure holding qusb2 phy attributes
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*
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* @phy: generic phy
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* @base: iomapped memory space for qubs2 phy
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*
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* @cfg_ahb_clk: AHB2PHY interface clock
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* @ref_clk: phy reference clock
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* @iface_clk: phy interface clock
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* @phy_reset: phy reset control
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* @vregs: regulator supplies bulk data
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*
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* @tcsr: TCSR syscon register map
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* @cell: nvmem cell containing phy tuning value
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*
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* @override_imp_res_offset: PHY should use different rescode offset
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* @imp_res_offset_value: rescode offset to be updated in IMP_CTRL1 register
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* @override_hstx_trim: PHY should use different HSTX o/p current value
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* @hstx_trim_value: HSTX_TRIM value to be updated in TUNE1 register
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* @override_preemphasis: PHY should use different pre-amphasis amplitude
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* @preemphasis_level: Amplitude Pre-Emphasis to be updated in TUNE1 register
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* @override_preemphasis_width: PHY should use different pre-emphasis duration
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* @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1
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*
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* @cfg: phy config data
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* @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme
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* @phy_initialized: indicate if PHY has been initialized
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* @mode: current PHY mode
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*/
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struct qusb2_phy {
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struct phy *phy;
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void __iomem *base;
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struct clk *cfg_ahb_clk;
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struct clk *ref_clk;
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struct clk *iface_clk;
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struct reset_control *phy_reset;
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struct regulator_bulk_data vregs[QUSB2_NUM_VREGS];
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struct regmap *tcsr;
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struct nvmem_cell *cell;
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bool override_imp_res_offset;
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u8 imp_res_offset_value;
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bool override_hstx_trim;
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u8 hstx_trim_value;
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bool override_preemphasis;
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u8 preemphasis_level;
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bool override_preemphasis_width;
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u8 preemphasis_width;
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const struct qusb2_phy_cfg *cfg;
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bool has_se_clk_scheme;
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bool phy_initialized;
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enum phy_mode mode;
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};
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static inline void qusb2_write_mask(void __iomem *base, u32 offset,
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u32 val, u32 mask)
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{
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u32 reg;
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reg = readl(base + offset);
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reg &= ~mask;
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reg |= val & mask;
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writel(reg, base + offset);
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/* Ensure above write is completed */
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readl(base + offset);
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}
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static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val)
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{
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u32 reg;
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reg = readl(base + offset);
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reg |= val;
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writel(reg, base + offset);
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/* Ensure above write is completed */
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readl(base + offset);
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}
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static inline void qusb2_clrbits(void __iomem *base, u32 offset, u32 val)
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{
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u32 reg;
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reg = readl(base + offset);
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reg &= ~val;
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writel(reg, base + offset);
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/* Ensure above write is completed */
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readl(base + offset);
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}
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static inline
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void qcom_qusb2_phy_configure(void __iomem *base,
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const unsigned int *regs,
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const struct qusb2_phy_init_tbl tbl[], int num)
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{
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int i;
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for (i = 0; i < num; i++) {
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if (tbl[i].in_layout)
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writel(tbl[i].val, base + regs[tbl[i].offset]);
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else
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writel(tbl[i].val, base + tbl[i].offset);
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}
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}
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/*
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* Update board specific PHY tuning override values if specified from
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* device tree.
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*/
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static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy)
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{
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const struct qusb2_phy_cfg *cfg = qphy->cfg;
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if (qphy->override_imp_res_offset)
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qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1,
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qphy->imp_res_offset_value << IMP_RES_OFFSET_SHIFT,
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IMP_RES_OFFSET_MASK);
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if (qphy->override_hstx_trim)
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qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
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qphy->hstx_trim_value << HSTX_TRIM_SHIFT,
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HSTX_TRIM_MASK);
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if (qphy->override_preemphasis)
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qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
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qphy->preemphasis_level << PREEMPHASIS_EN_SHIFT,
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PREEMPHASIS_EN_MASK);
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if (qphy->override_preemphasis_width) {
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if (qphy->preemphasis_width ==
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QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT)
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qusb2_setbits(qphy->base,
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cfg->regs[QUSB2PHY_PORT_TUNE1],
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PREEMPH_WIDTH_HALF_BIT);
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else
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qusb2_clrbits(qphy->base,
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cfg->regs[QUSB2PHY_PORT_TUNE1],
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PREEMPH_WIDTH_HALF_BIT);
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}
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}
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/*
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* Fetches HS Tx tuning value from nvmem and sets the
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* QUSB2PHY_PORT_TUNE1/2 register.
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* For error case, skip setting the value and use the default value.
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*/
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static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
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{
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struct device *dev = &qphy->phy->dev;
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const struct qusb2_phy_cfg *cfg = qphy->cfg;
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u8 *val;
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/* efuse register is optional */
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if (!qphy->cell)
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return;
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/*
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* Read efuse register having TUNE2/1 parameter's high nibble.
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* If efuse register shows value as 0x0, or if we fail to find
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* a valid efuse register settings, then use default value
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* as 0xB for high nibble that we have already set while
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* configuring phy.
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*/
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val = nvmem_cell_read(qphy->cell, NULL);
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if (IS_ERR(val) || !val[0]) {
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dev_dbg(dev, "failed to read a valid hs-tx trim value\n");
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return;
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}
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/* Fused TUNE1/2 value is the higher nibble only */
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if (cfg->update_tune1_with_efuse)
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qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
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val[0] << 0x4);
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else
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qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
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val[0] << 0x4);
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}
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static int qusb2_phy_set_mode(struct phy *phy, enum phy_mode mode)
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{
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struct qusb2_phy *qphy = phy_get_drvdata(phy);
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qphy->mode = mode;
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return 0;
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}
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static int __maybe_unused qusb2_phy_runtime_suspend(struct device *dev)
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{
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struct qusb2_phy *qphy = dev_get_drvdata(dev);
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const struct qusb2_phy_cfg *cfg = qphy->cfg;
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u32 intr_mask;
|
|
|
|
dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode);
|
|
|
|
if (!qphy->phy_initialized) {
|
|
dev_vdbg(dev, "PHY not initialized, bailing out\n");
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Enable DP/DM interrupts to detect line state changes based on current
|
|
* speed. In other words, enable the triggers _opposite_ of what the
|
|
* current D+/D- levels are e.g. if currently D+ high, D- low
|
|
* (HS 'J'/Suspend), configure the mask to trigger on D+ low OR D- high
|
|
*/
|
|
intr_mask = DPSE_INTR_EN | DMSE_INTR_EN;
|
|
switch (qphy->mode) {
|
|
case PHY_MODE_USB_HOST_HS:
|
|
case PHY_MODE_USB_HOST_FS:
|
|
case PHY_MODE_USB_DEVICE_HS:
|
|
case PHY_MODE_USB_DEVICE_FS:
|
|
intr_mask |= DMSE_INTR_HIGH_SEL;
|
|
break;
|
|
case PHY_MODE_USB_HOST_LS:
|
|
case PHY_MODE_USB_DEVICE_LS:
|
|
intr_mask |= DPSE_INTR_HIGH_SEL;
|
|
break;
|
|
default:
|
|
/* No device connected, enable both DP/DM high interrupt */
|
|
intr_mask |= DMSE_INTR_HIGH_SEL;
|
|
intr_mask |= DPSE_INTR_HIGH_SEL;
|
|
break;
|
|
}
|
|
|
|
writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
|
|
|
|
/* hold core PLL into reset */
|
|
if (cfg->has_pll_override) {
|
|
qusb2_setbits(qphy->base,
|
|
cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE],
|
|
CORE_PLL_EN_FROM_RESET | CORE_RESET |
|
|
CORE_RESET_MUX);
|
|
}
|
|
|
|
/* enable phy auto-resume only if device is connected on bus */
|
|
if (qphy->mode != PHY_MODE_INVALID) {
|
|
qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
|
|
cfg->autoresume_en);
|
|
/* Autoresume bit has to be toggled in order to enable it */
|
|
qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
|
|
cfg->autoresume_en);
|
|
}
|
|
|
|
if (!qphy->has_se_clk_scheme)
|
|
clk_disable_unprepare(qphy->ref_clk);
|
|
|
|
clk_disable_unprepare(qphy->cfg_ahb_clk);
|
|
clk_disable_unprepare(qphy->iface_clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused qusb2_phy_runtime_resume(struct device *dev)
|
|
{
|
|
struct qusb2_phy *qphy = dev_get_drvdata(dev);
|
|
const struct qusb2_phy_cfg *cfg = qphy->cfg;
|
|
int ret;
|
|
|
|
dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode);
|
|
|
|
if (!qphy->phy_initialized) {
|
|
dev_vdbg(dev, "PHY not initialized, bailing out\n");
|
|
return 0;
|
|
}
|
|
|
|
ret = clk_prepare_enable(qphy->iface_clk);
|
|
if (ret) {
|
|
dev_err(dev, "failed to enable iface_clk, %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = clk_prepare_enable(qphy->cfg_ahb_clk);
|
|
if (ret) {
|
|
dev_err(dev, "failed to enable cfg ahb clock, %d\n", ret);
|
|
goto disable_iface_clk;
|
|
}
|
|
|
|
if (!qphy->has_se_clk_scheme) {
|
|
clk_prepare_enable(qphy->ref_clk);
|
|
if (ret) {
|
|
dev_err(dev, "failed to enable ref clk, %d\n", ret);
|
|
goto disable_ahb_clk;
|
|
}
|
|
}
|
|
|
|
writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
|
|
|
|
/* bring core PLL out of reset */
|
|
if (cfg->has_pll_override) {
|
|
qusb2_clrbits(qphy->base,
|
|
cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE],
|
|
CORE_RESET | CORE_RESET_MUX);
|
|
}
|
|
|
|
return 0;
|
|
|
|
disable_ahb_clk:
|
|
clk_disable_unprepare(qphy->cfg_ahb_clk);
|
|
disable_iface_clk:
|
|
clk_disable_unprepare(qphy->iface_clk);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int qusb2_phy_init(struct phy *phy)
|
|
{
|
|
struct qusb2_phy *qphy = phy_get_drvdata(phy);
|
|
const struct qusb2_phy_cfg *cfg = qphy->cfg;
|
|
unsigned int val = 0;
|
|
unsigned int clk_scheme;
|
|
int ret;
|
|
|
|
dev_vdbg(&phy->dev, "%s(): Initializing QUSB2 phy\n", __func__);
|
|
|
|
/* turn on regulator supplies */
|
|
ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = clk_prepare_enable(qphy->iface_clk);
|
|
if (ret) {
|
|
dev_err(&phy->dev, "failed to enable iface_clk, %d\n", ret);
|
|
goto poweroff_phy;
|
|
}
|
|
|
|
/* enable ahb interface clock to program phy */
|
|
ret = clk_prepare_enable(qphy->cfg_ahb_clk);
|
|
if (ret) {
|
|
dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret);
|
|
goto disable_iface_clk;
|
|
}
|
|
|
|
/* Perform phy reset */
|
|
ret = reset_control_assert(qphy->phy_reset);
|
|
if (ret) {
|
|
dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret);
|
|
goto disable_ahb_clk;
|
|
}
|
|
|
|
/* 100 us delay to keep PHY in reset mode */
|
|
usleep_range(100, 150);
|
|
|
|
ret = reset_control_deassert(qphy->phy_reset);
|
|
if (ret) {
|
|
dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret);
|
|
goto disable_ahb_clk;
|
|
}
|
|
|
|
/* Disable the PHY */
|
|
qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],
|
|
qphy->cfg->disable_ctrl);
|
|
|
|
if (cfg->has_pll_test) {
|
|
/* save reset value to override reference clock scheme later */
|
|
val = readl(qphy->base + QUSB2PHY_PLL_TEST);
|
|
}
|
|
|
|
qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl,
|
|
cfg->tbl_num);
|
|
|
|
/* Override board specific PHY tuning values */
|
|
qusb2_phy_override_phy_params(qphy);
|
|
|
|
/* Set efuse value for tuning the PHY */
|
|
qusb2_phy_set_tune2_param(qphy);
|
|
|
|
/* Enable the PHY */
|
|
qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],
|
|
POWER_DOWN);
|
|
|
|
/* Required to get phy pll lock successfully */
|
|
usleep_range(150, 160);
|
|
|
|
/* Default is single-ended clock on msm8996 */
|
|
qphy->has_se_clk_scheme = true;
|
|
/*
|
|
* read TCSR_PHY_CLK_SCHEME register to check if single-ended
|
|
* clock scheme is selected. If yes, then disable differential
|
|
* ref_clk and use single-ended clock, otherwise use differential
|
|
* ref_clk only.
|
|
*/
|
|
if (qphy->tcsr) {
|
|
ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset,
|
|
&clk_scheme);
|
|
if (ret) {
|
|
dev_err(&phy->dev, "failed to read clk scheme reg\n");
|
|
goto assert_phy_reset;
|
|
}
|
|
|
|
/* is it a differential clock scheme ? */
|
|
if (!(clk_scheme & PHY_CLK_SCHEME_SEL)) {
|
|
dev_vdbg(&phy->dev, "%s(): select differential clk\n",
|
|
__func__);
|
|
qphy->has_se_clk_scheme = false;
|
|
} else {
|
|
dev_vdbg(&phy->dev, "%s(): select single-ended clk\n",
|
|
__func__);
|
|
}
|
|
}
|
|
|
|
if (!qphy->has_se_clk_scheme) {
|
|
ret = clk_prepare_enable(qphy->ref_clk);
|
|
if (ret) {
|
|
dev_err(&phy->dev, "failed to enable ref clk, %d\n",
|
|
ret);
|
|
goto assert_phy_reset;
|
|
}
|
|
}
|
|
|
|
if (cfg->has_pll_test) {
|
|
if (!qphy->has_se_clk_scheme)
|
|
val &= ~CLK_REF_SEL;
|
|
else
|
|
val |= CLK_REF_SEL;
|
|
|
|
writel(val, qphy->base + QUSB2PHY_PLL_TEST);
|
|
|
|
/* ensure above write is through */
|
|
readl(qphy->base + QUSB2PHY_PLL_TEST);
|
|
}
|
|
|
|
/* Required to get phy pll lock successfully */
|
|
usleep_range(100, 110);
|
|
|
|
val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]);
|
|
if (!(val & cfg->mask_core_ready)) {
|
|
dev_err(&phy->dev,
|
|
"QUSB2PHY pll lock failed: status reg = %x\n", val);
|
|
ret = -EBUSY;
|
|
goto disable_ref_clk;
|
|
}
|
|
qphy->phy_initialized = true;
|
|
|
|
return 0;
|
|
|
|
disable_ref_clk:
|
|
if (!qphy->has_se_clk_scheme)
|
|
clk_disable_unprepare(qphy->ref_clk);
|
|
assert_phy_reset:
|
|
reset_control_assert(qphy->phy_reset);
|
|
disable_ahb_clk:
|
|
clk_disable_unprepare(qphy->cfg_ahb_clk);
|
|
disable_iface_clk:
|
|
clk_disable_unprepare(qphy->iface_clk);
|
|
poweroff_phy:
|
|
regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int qusb2_phy_exit(struct phy *phy)
|
|
{
|
|
struct qusb2_phy *qphy = phy_get_drvdata(phy);
|
|
|
|
/* Disable the PHY */
|
|
qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN],
|
|
qphy->cfg->disable_ctrl);
|
|
|
|
if (!qphy->has_se_clk_scheme)
|
|
clk_disable_unprepare(qphy->ref_clk);
|
|
|
|
reset_control_assert(qphy->phy_reset);
|
|
|
|
clk_disable_unprepare(qphy->cfg_ahb_clk);
|
|
clk_disable_unprepare(qphy->iface_clk);
|
|
|
|
regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
|
|
|
|
qphy->phy_initialized = false;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct phy_ops qusb2_phy_gen_ops = {
|
|
.init = qusb2_phy_init,
|
|
.exit = qusb2_phy_exit,
|
|
.set_mode = qusb2_phy_set_mode,
|
|
.owner = THIS_MODULE,
|
|
};
|
|
|
|
static const struct of_device_id qusb2_phy_of_match_table[] = {
|
|
{
|
|
.compatible = "qcom,msm8996-qusb2-phy",
|
|
.data = &msm8996_phy_cfg,
|
|
}, {
|
|
.compatible = "qcom,sdm845-qusb2-phy",
|
|
.data = &sdm845_phy_cfg,
|
|
},
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, qusb2_phy_of_match_table);
|
|
|
|
static const struct dev_pm_ops qusb2_phy_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(qusb2_phy_runtime_suspend,
|
|
qusb2_phy_runtime_resume, NULL)
|
|
};
|
|
|
|
static int qusb2_phy_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct qusb2_phy *qphy;
|
|
struct phy_provider *phy_provider;
|
|
struct phy *generic_phy;
|
|
struct resource *res;
|
|
int ret, i;
|
|
int num;
|
|
u32 value;
|
|
|
|
qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
|
|
if (!qphy)
|
|
return -ENOMEM;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
qphy->base = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(qphy->base))
|
|
return PTR_ERR(qphy->base);
|
|
|
|
qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb");
|
|
if (IS_ERR(qphy->cfg_ahb_clk)) {
|
|
ret = PTR_ERR(qphy->cfg_ahb_clk);
|
|
if (ret != -EPROBE_DEFER)
|
|
dev_err(dev, "failed to get cfg ahb clk, %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
qphy->ref_clk = devm_clk_get(dev, "ref");
|
|
if (IS_ERR(qphy->ref_clk)) {
|
|
ret = PTR_ERR(qphy->ref_clk);
|
|
if (ret != -EPROBE_DEFER)
|
|
dev_err(dev, "failed to get ref clk, %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
qphy->iface_clk = devm_clk_get(dev, "iface");
|
|
if (IS_ERR(qphy->iface_clk)) {
|
|
ret = PTR_ERR(qphy->iface_clk);
|
|
if (ret == -EPROBE_DEFER)
|
|
return ret;
|
|
qphy->iface_clk = NULL;
|
|
dev_dbg(dev, "failed to get iface clk, %d\n", ret);
|
|
}
|
|
|
|
qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0);
|
|
if (IS_ERR(qphy->phy_reset)) {
|
|
dev_err(dev, "failed to get phy core reset\n");
|
|
return PTR_ERR(qphy->phy_reset);
|
|
}
|
|
|
|
num = ARRAY_SIZE(qphy->vregs);
|
|
for (i = 0; i < num; i++)
|
|
qphy->vregs[i].supply = qusb2_phy_vreg_names[i];
|
|
|
|
ret = devm_regulator_bulk_get(dev, num, qphy->vregs);
|
|
if (ret) {
|
|
if (ret != -EPROBE_DEFER)
|
|
dev_err(dev, "failed to get regulator supplies: %d\n",
|
|
ret);
|
|
return ret;
|
|
}
|
|
|
|
/* Get the specific init parameters of QMP phy */
|
|
qphy->cfg = of_device_get_match_data(dev);
|
|
|
|
qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node,
|
|
"qcom,tcsr-syscon");
|
|
if (IS_ERR(qphy->tcsr)) {
|
|
dev_dbg(dev, "failed to lookup TCSR regmap\n");
|
|
qphy->tcsr = NULL;
|
|
}
|
|
|
|
qphy->cell = devm_nvmem_cell_get(dev, NULL);
|
|
if (IS_ERR(qphy->cell)) {
|
|
if (PTR_ERR(qphy->cell) == -EPROBE_DEFER)
|
|
return -EPROBE_DEFER;
|
|
qphy->cell = NULL;
|
|
dev_dbg(dev, "failed to lookup tune2 hstx trim value\n");
|
|
}
|
|
|
|
if (!of_property_read_u32(dev->of_node, "qcom,imp-res-offset-value",
|
|
&value)) {
|
|
qphy->imp_res_offset_value = (u8)value;
|
|
qphy->override_imp_res_offset = true;
|
|
}
|
|
|
|
if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value",
|
|
&value)) {
|
|
qphy->hstx_trim_value = (u8)value;
|
|
qphy->override_hstx_trim = true;
|
|
}
|
|
|
|
if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-level",
|
|
&value)) {
|
|
qphy->preemphasis_level = (u8)value;
|
|
qphy->override_preemphasis = true;
|
|
}
|
|
|
|
if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-width",
|
|
&value)) {
|
|
qphy->preemphasis_width = (u8)value;
|
|
qphy->override_preemphasis_width = true;
|
|
}
|
|
|
|
pm_runtime_set_active(dev);
|
|
pm_runtime_enable(dev);
|
|
/*
|
|
* Prevent runtime pm from being ON by default. Users can enable
|
|
* it using power/control in sysfs.
|
|
*/
|
|
pm_runtime_forbid(dev);
|
|
|
|
generic_phy = devm_phy_create(dev, NULL, &qusb2_phy_gen_ops);
|
|
if (IS_ERR(generic_phy)) {
|
|
ret = PTR_ERR(generic_phy);
|
|
dev_err(dev, "failed to create phy, %d\n", ret);
|
|
pm_runtime_disable(dev);
|
|
return ret;
|
|
}
|
|
qphy->phy = generic_phy;
|
|
|
|
dev_set_drvdata(dev, qphy);
|
|
phy_set_drvdata(generic_phy, qphy);
|
|
|
|
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
|
if (!IS_ERR(phy_provider))
|
|
dev_info(dev, "Registered Qcom-QUSB2 phy\n");
|
|
else
|
|
pm_runtime_disable(dev);
|
|
|
|
return PTR_ERR_OR_ZERO(phy_provider);
|
|
}
|
|
|
|
static struct platform_driver qusb2_phy_driver = {
|
|
.probe = qusb2_phy_probe,
|
|
.driver = {
|
|
.name = "qcom-qusb2-phy",
|
|
.pm = &qusb2_phy_pm_ops,
|
|
.of_match_table = qusb2_phy_of_match_table,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(qusb2_phy_driver);
|
|
|
|
MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
|
|
MODULE_DESCRIPTION("Qualcomm QUSB2 PHY driver");
|
|
MODULE_LICENSE("GPL v2");
|