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![Kunihiko Hayashi](/assets/img/avatar_default.png)
Add a driver for PHY interface built into USB3 controller implemented in UniPhier SoCs. This driver supports High-Speed PHY and Super-Speed PHY. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Motoya Tanigawa <tanigawa.motoya@socionext.com> Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
349 lines
8.7 KiB
C
349 lines
8.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* phy-uniphier-usb3ss.c - SS-PHY driver for Socionext UniPhier USB3 controller
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* Copyright 2015-2018 Socionext Inc.
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* Author:
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* Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
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* Contributors:
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* Motoya Tanigawa <tanigawa.motoya@socionext.com>
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* Masami Hiramatsu <masami.hiramatsu@linaro.org>
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*/
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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#define SSPHY_TESTI 0x0
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#define SSPHY_TESTO 0x4
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#define TESTI_DAT_MASK GENMASK(13, 6)
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#define TESTI_ADR_MASK GENMASK(5, 1)
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#define TESTI_WR_EN BIT(0)
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#define PHY_F(regno, msb, lsb) { (regno), (msb), (lsb) }
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#define CDR_CPD_TRIM PHY_F(7, 3, 0) /* RxPLL charge pump current */
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#define CDR_CPF_TRIM PHY_F(8, 3, 0) /* RxPLL charge pump current 2 */
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#define TX_PLL_TRIM PHY_F(9, 3, 0) /* TxPLL charge pump current */
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#define BGAP_TRIM PHY_F(11, 3, 0) /* Bandgap voltage */
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#define CDR_TRIM PHY_F(13, 6, 5) /* Clock Data Recovery setting */
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#define VCO_CTRL PHY_F(26, 7, 4) /* VCO control */
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#define VCOPLL_CTRL PHY_F(27, 2, 0) /* TxPLL VCO tuning */
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#define VCOPLL_CM PHY_F(28, 1, 0) /* TxPLL voltage */
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#define MAX_PHY_PARAMS 7
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struct uniphier_u3ssphy_param {
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struct {
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int reg_no;
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int msb;
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int lsb;
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} field;
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u8 value;
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};
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struct uniphier_u3ssphy_priv {
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struct device *dev;
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void __iomem *base;
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struct clk *clk, *clk_ext, *clk_parent, *clk_parent_gio;
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struct reset_control *rst, *rst_parent, *rst_parent_gio;
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struct regulator *vbus;
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const struct uniphier_u3ssphy_soc_data *data;
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};
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struct uniphier_u3ssphy_soc_data {
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bool is_legacy;
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int nparams;
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const struct uniphier_u3ssphy_param param[MAX_PHY_PARAMS];
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};
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static void uniphier_u3ssphy_testio_write(struct uniphier_u3ssphy_priv *priv,
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u32 data)
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{
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/* need to read TESTO twice after accessing TESTI */
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writel(data, priv->base + SSPHY_TESTI);
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readl(priv->base + SSPHY_TESTO);
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readl(priv->base + SSPHY_TESTO);
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}
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static void uniphier_u3ssphy_set_param(struct uniphier_u3ssphy_priv *priv,
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const struct uniphier_u3ssphy_param *p)
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{
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u32 val;
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u8 field_mask = GENMASK(p->field.msb, p->field.lsb);
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u8 data;
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/* read previous data */
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val = FIELD_PREP(TESTI_DAT_MASK, 1);
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val |= FIELD_PREP(TESTI_ADR_MASK, p->field.reg_no);
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uniphier_u3ssphy_testio_write(priv, val);
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val = readl(priv->base + SSPHY_TESTO);
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/* update value */
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val &= ~FIELD_PREP(TESTI_DAT_MASK, field_mask);
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data = field_mask & (p->value << p->field.lsb);
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val = FIELD_PREP(TESTI_DAT_MASK, data);
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val |= FIELD_PREP(TESTI_ADR_MASK, p->field.reg_no);
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uniphier_u3ssphy_testio_write(priv, val);
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uniphier_u3ssphy_testio_write(priv, val | TESTI_WR_EN);
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uniphier_u3ssphy_testio_write(priv, val);
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/* read current data as dummy */
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val = FIELD_PREP(TESTI_DAT_MASK, 1);
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val |= FIELD_PREP(TESTI_ADR_MASK, p->field.reg_no);
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uniphier_u3ssphy_testio_write(priv, val);
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readl(priv->base + SSPHY_TESTO);
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}
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static int uniphier_u3ssphy_power_on(struct phy *phy)
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{
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struct uniphier_u3ssphy_priv *priv = phy_get_drvdata(phy);
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int ret;
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ret = clk_prepare_enable(priv->clk_ext);
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if (ret)
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return ret;
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ret = clk_prepare_enable(priv->clk);
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if (ret)
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goto out_clk_ext_disable;
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ret = reset_control_deassert(priv->rst);
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if (ret)
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goto out_clk_disable;
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if (priv->vbus) {
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ret = regulator_enable(priv->vbus);
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if (ret)
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goto out_rst_assert;
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}
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return 0;
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out_rst_assert:
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reset_control_assert(priv->rst);
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out_clk_disable:
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clk_disable_unprepare(priv->clk);
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out_clk_ext_disable:
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clk_disable_unprepare(priv->clk_ext);
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return ret;
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}
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static int uniphier_u3ssphy_power_off(struct phy *phy)
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{
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struct uniphier_u3ssphy_priv *priv = phy_get_drvdata(phy);
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if (priv->vbus)
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regulator_disable(priv->vbus);
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reset_control_assert(priv->rst);
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clk_disable_unprepare(priv->clk);
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clk_disable_unprepare(priv->clk_ext);
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return 0;
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}
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static int uniphier_u3ssphy_init(struct phy *phy)
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{
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struct uniphier_u3ssphy_priv *priv = phy_get_drvdata(phy);
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int i, ret;
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ret = clk_prepare_enable(priv->clk_parent);
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if (ret)
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return ret;
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ret = clk_prepare_enable(priv->clk_parent_gio);
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if (ret)
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goto out_clk_disable;
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ret = reset_control_deassert(priv->rst_parent);
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if (ret)
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goto out_clk_gio_disable;
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ret = reset_control_deassert(priv->rst_parent_gio);
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if (ret)
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goto out_rst_assert;
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if (priv->data->is_legacy)
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return 0;
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for (i = 0; i < priv->data->nparams; i++)
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uniphier_u3ssphy_set_param(priv, &priv->data->param[i]);
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return 0;
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out_rst_assert:
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reset_control_assert(priv->rst_parent);
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out_clk_gio_disable:
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clk_disable_unprepare(priv->clk_parent_gio);
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out_clk_disable:
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clk_disable_unprepare(priv->clk_parent);
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return ret;
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}
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static int uniphier_u3ssphy_exit(struct phy *phy)
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{
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struct uniphier_u3ssphy_priv *priv = phy_get_drvdata(phy);
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reset_control_assert(priv->rst_parent_gio);
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reset_control_assert(priv->rst_parent);
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clk_disable_unprepare(priv->clk_parent_gio);
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clk_disable_unprepare(priv->clk_parent);
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return 0;
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}
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static const struct phy_ops uniphier_u3ssphy_ops = {
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.init = uniphier_u3ssphy_init,
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.exit = uniphier_u3ssphy_exit,
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.power_on = uniphier_u3ssphy_power_on,
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.power_off = uniphier_u3ssphy_power_off,
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.owner = THIS_MODULE,
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};
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static int uniphier_u3ssphy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct uniphier_u3ssphy_priv *priv;
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struct phy_provider *phy_provider;
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struct resource *res;
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struct phy *phy;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->dev = dev;
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priv->data = of_device_get_match_data(dev);
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if (WARN_ON(!priv->data ||
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priv->data->nparams > MAX_PHY_PARAMS))
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return -EINVAL;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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if (!priv->data->is_legacy) {
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priv->clk = devm_clk_get(dev, "phy");
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if (IS_ERR(priv->clk))
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return PTR_ERR(priv->clk);
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priv->clk_ext = devm_clk_get(dev, "phy-ext");
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if (IS_ERR(priv->clk_ext)) {
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if (PTR_ERR(priv->clk_ext) == -ENOENT)
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priv->clk_ext = NULL;
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else
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return PTR_ERR(priv->clk_ext);
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}
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priv->rst = devm_reset_control_get_shared(dev, "phy");
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if (IS_ERR(priv->rst))
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return PTR_ERR(priv->rst);
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} else {
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priv->clk_parent_gio = devm_clk_get(dev, "gio");
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if (IS_ERR(priv->clk_parent_gio))
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return PTR_ERR(priv->clk_parent_gio);
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priv->rst_parent_gio =
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devm_reset_control_get_shared(dev, "gio");
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if (IS_ERR(priv->rst_parent_gio))
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return PTR_ERR(priv->rst_parent_gio);
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}
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priv->clk_parent = devm_clk_get(dev, "link");
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if (IS_ERR(priv->clk_parent))
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return PTR_ERR(priv->clk_parent);
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priv->rst_parent = devm_reset_control_get_shared(dev, "link");
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if (IS_ERR(priv->rst_parent))
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return PTR_ERR(priv->rst_parent);
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priv->vbus = devm_regulator_get_optional(dev, "vbus");
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if (IS_ERR(priv->vbus)) {
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if (PTR_ERR(priv->vbus) == -EPROBE_DEFER)
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return PTR_ERR(priv->vbus);
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priv->vbus = NULL;
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}
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phy = devm_phy_create(dev, dev->of_node, &uniphier_u3ssphy_ops);
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if (IS_ERR(phy))
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return PTR_ERR(phy);
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phy_set_drvdata(phy, priv);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static const struct uniphier_u3ssphy_soc_data uniphier_pro4_data = {
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.is_legacy = true,
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};
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static const struct uniphier_u3ssphy_soc_data uniphier_pxs2_data = {
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.is_legacy = false,
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.nparams = 7,
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.param = {
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{ CDR_CPD_TRIM, 10 },
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{ CDR_CPF_TRIM, 3 },
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{ TX_PLL_TRIM, 5 },
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{ BGAP_TRIM, 9 },
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{ CDR_TRIM, 2 },
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{ VCOPLL_CTRL, 7 },
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{ VCOPLL_CM, 1 },
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},
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};
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static const struct uniphier_u3ssphy_soc_data uniphier_ld20_data = {
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.is_legacy = false,
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.nparams = 3,
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.param = {
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{ CDR_CPD_TRIM, 6 },
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{ CDR_TRIM, 2 },
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{ VCO_CTRL, 5 },
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},
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};
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static const struct of_device_id uniphier_u3ssphy_match[] = {
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{
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.compatible = "socionext,uniphier-pro4-usb3-ssphy",
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.data = &uniphier_pro4_data,
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},
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{
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.compatible = "socionext,uniphier-pxs2-usb3-ssphy",
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.data = &uniphier_pxs2_data,
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},
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{
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.compatible = "socionext,uniphier-ld20-usb3-ssphy",
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.data = &uniphier_ld20_data,
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},
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{
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.compatible = "socionext,uniphier-pxs3-usb3-ssphy",
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.data = &uniphier_ld20_data,
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},
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, uniphier_u3ssphy_match);
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static struct platform_driver uniphier_u3ssphy_driver = {
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.probe = uniphier_u3ssphy_probe,
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.driver = {
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.name = "uniphier-usb3-ssphy",
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.of_match_table = uniphier_u3ssphy_match,
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},
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};
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module_platform_driver(uniphier_u3ssphy_driver);
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MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
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MODULE_DESCRIPTION("UniPhier SS-PHY driver for USB3 controller");
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MODULE_LICENSE("GPL v2");
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