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![Maxime Jourdan](/assets/img/avatar_default.png)
Amlogic SoCs have a repository of 256 canvas which they use to describe pixel buffers. They contain metadata like width, height, block mode, endianness [..] Many IPs within those SoCs like vdec/vpu rely on those canvas to read/write pixels. Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
185 lines
4.6 KiB
C
185 lines
4.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 BayLibre, SAS
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* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
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* Copyright (C) 2014 Endless Mobile
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*/
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include <linux/soc/amlogic/meson-canvas.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/io.h>
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#define NUM_CANVAS 256
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/* DMC Registers */
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#define DMC_CAV_LUT_DATAL 0x00
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#define CANVAS_WIDTH_LBIT 29
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#define CANVAS_WIDTH_LWID 3
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#define DMC_CAV_LUT_DATAH 0x04
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#define CANVAS_WIDTH_HBIT 0
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#define CANVAS_HEIGHT_BIT 9
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#define CANVAS_WRAP_BIT 22
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#define CANVAS_BLKMODE_BIT 24
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#define CANVAS_ENDIAN_BIT 26
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#define DMC_CAV_LUT_ADDR 0x08
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#define CANVAS_LUT_WR_EN BIT(9)
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#define CANVAS_LUT_RD_EN BIT(8)
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struct meson_canvas {
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struct device *dev;
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void __iomem *reg_base;
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spinlock_t lock; /* canvas device lock */
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u8 used[NUM_CANVAS];
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};
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static void canvas_write(struct meson_canvas *canvas, u32 reg, u32 val)
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{
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writel_relaxed(val, canvas->reg_base + reg);
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}
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static u32 canvas_read(struct meson_canvas *canvas, u32 reg)
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{
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return readl_relaxed(canvas->reg_base + reg);
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}
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struct meson_canvas *meson_canvas_get(struct device *dev)
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{
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struct device_node *canvas_node;
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struct platform_device *canvas_pdev;
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canvas_node = of_parse_phandle(dev->of_node, "amlogic,canvas", 0);
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if (!canvas_node)
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return ERR_PTR(-ENODEV);
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canvas_pdev = of_find_device_by_node(canvas_node);
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if (!canvas_pdev)
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return ERR_PTR(-EPROBE_DEFER);
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return dev_get_drvdata(&canvas_pdev->dev);
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}
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EXPORT_SYMBOL_GPL(meson_canvas_get);
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int meson_canvas_config(struct meson_canvas *canvas, u8 canvas_index,
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u32 addr, u32 stride, u32 height,
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unsigned int wrap,
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unsigned int blkmode,
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unsigned int endian)
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{
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unsigned long flags;
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spin_lock_irqsave(&canvas->lock, flags);
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if (!canvas->used[canvas_index]) {
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dev_err(canvas->dev,
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"Trying to setup non allocated canvas %u\n",
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canvas_index);
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spin_unlock_irqrestore(&canvas->lock, flags);
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return -EINVAL;
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}
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canvas_write(canvas, DMC_CAV_LUT_DATAL,
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((addr + 7) >> 3) |
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(((stride + 7) >> 3) << CANVAS_WIDTH_LBIT));
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canvas_write(canvas, DMC_CAV_LUT_DATAH,
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((((stride + 7) >> 3) >> CANVAS_WIDTH_LWID) <<
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CANVAS_WIDTH_HBIT) |
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(height << CANVAS_HEIGHT_BIT) |
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(wrap << CANVAS_WRAP_BIT) |
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(blkmode << CANVAS_BLKMODE_BIT) |
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(endian << CANVAS_ENDIAN_BIT));
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canvas_write(canvas, DMC_CAV_LUT_ADDR,
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CANVAS_LUT_WR_EN | canvas_index);
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/* Force a read-back to make sure everything is flushed. */
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canvas_read(canvas, DMC_CAV_LUT_DATAH);
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spin_unlock_irqrestore(&canvas->lock, flags);
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return 0;
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}
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EXPORT_SYMBOL_GPL(meson_canvas_config);
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int meson_canvas_alloc(struct meson_canvas *canvas, u8 *canvas_index)
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{
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int i;
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unsigned long flags;
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spin_lock_irqsave(&canvas->lock, flags);
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for (i = 0; i < NUM_CANVAS; ++i) {
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if (!canvas->used[i]) {
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canvas->used[i] = 1;
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spin_unlock_irqrestore(&canvas->lock, flags);
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*canvas_index = i;
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return 0;
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}
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}
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spin_unlock_irqrestore(&canvas->lock, flags);
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dev_err(canvas->dev, "No more canvas available\n");
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return -ENODEV;
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}
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EXPORT_SYMBOL_GPL(meson_canvas_alloc);
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int meson_canvas_free(struct meson_canvas *canvas, u8 canvas_index)
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{
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unsigned long flags;
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spin_lock_irqsave(&canvas->lock, flags);
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if (!canvas->used[canvas_index]) {
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dev_err(canvas->dev,
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"Trying to free unused canvas %u\n", canvas_index);
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spin_unlock_irqrestore(&canvas->lock, flags);
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return -EINVAL;
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}
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canvas->used[canvas_index] = 0;
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spin_unlock_irqrestore(&canvas->lock, flags);
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return 0;
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}
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EXPORT_SYMBOL_GPL(meson_canvas_free);
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static int meson_canvas_probe(struct platform_device *pdev)
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{
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struct resource *res;
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struct meson_canvas *canvas;
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struct device *dev = &pdev->dev;
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canvas = devm_kzalloc(dev, sizeof(*canvas), GFP_KERNEL);
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if (!canvas)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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canvas->reg_base = devm_ioremap_resource(dev, res);
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if (IS_ERR(canvas->reg_base))
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return PTR_ERR(canvas->reg_base);
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canvas->dev = dev;
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spin_lock_init(&canvas->lock);
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dev_set_drvdata(dev, canvas);
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return 0;
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}
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static const struct of_device_id canvas_dt_match[] = {
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{ .compatible = "amlogic,canvas" },
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{}
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};
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MODULE_DEVICE_TABLE(of, canvas_dt_match);
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static struct platform_driver meson_canvas_driver = {
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.probe = meson_canvas_probe,
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.driver = {
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.name = "amlogic-canvas",
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.of_match_table = canvas_dt_match,
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},
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};
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module_platform_driver(meson_canvas_driver);
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MODULE_DESCRIPTION("Amlogic Canvas driver");
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MODULE_AUTHOR("Maxime Jourdan <mjourdan@baylibre.com>");
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MODULE_LICENSE("GPL");
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