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![Dan Carpenter](/assets/img/avatar_default.png)
The MESON_AO_RPROC_SRAM_USABLE_BITS macro is used like this:
if (priv->sram_pa & ~MESON_AO_RPROC_SRAM_USABLE_BITS) {
dev_err(dev, "SRAM address contains unusable bits\n");
The problem is that "->sram_pa" is type phys_addr_t which is potentially
64 bits. That means the MESON_AO_RPROC_SRAM_USABLE_BITS macro needs to
be a 64 bit type as well to ensure that high 32 bits are cleared.
Fixes: 6cb58ea897
("remoteproc: meson-mx-ao-arc: Add a driver for the AO ARC remote procesor")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211004105257.GA27301@kili
261 lines
7.1 KiB
C
261 lines
7.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2020 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/genalloc.h>
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#include <linux/regmap.h>
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#include <linux/remoteproc.h>
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#include <linux/reset.h>
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#include <linux/sizes.h>
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#include "remoteproc_internal.h"
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#define AO_REMAP_REG0 0x0
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#define AO_REMAP_REG0_REMAP_AHB_SRAM_BITS_17_14_FOR_ARM_CPU GENMASK(3, 0)
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#define AO_REMAP_REG1 0x4
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#define AO_REMAP_REG1_MOVE_AHB_SRAM_TO_0X0_INSTEAD_OF_DDR BIT(4)
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#define AO_REMAP_REG1_REMAP_AHB_SRAM_BITS_17_14_FOR_MEDIA_CPU GENMASK(3, 0)
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#define AO_CPU_CNTL 0x0
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#define AO_CPU_CNTL_AHB_SRAM_BITS_31_20 GENMASK(28, 16)
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#define AO_CPU_CNTL_HALT BIT(9)
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#define AO_CPU_CNTL_UNKNONWN BIT(8)
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#define AO_CPU_CNTL_RUN BIT(0)
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#define AO_CPU_STAT 0x4
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#define AO_SECURE_REG0 0x0
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#define AO_SECURE_REG0_AHB_SRAM_BITS_19_12 GENMASK(15, 8)
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/* Only bits [31:20] and [17:14] are usable, all other bits must be zero */
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#define MESON_AO_RPROC_SRAM_USABLE_BITS 0xfff3c000ULL
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#define MESON_AO_RPROC_MEMORY_OFFSET 0x10000000
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struct meson_mx_ao_arc_rproc_priv {
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void __iomem *remap_base;
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void __iomem *cpu_base;
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unsigned long sram_va;
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phys_addr_t sram_pa;
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size_t sram_size;
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struct gen_pool *sram_pool;
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struct reset_control *arc_reset;
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struct clk *arc_pclk;
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struct regmap *secbus2_regmap;
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};
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static int meson_mx_ao_arc_rproc_start(struct rproc *rproc)
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{
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struct meson_mx_ao_arc_rproc_priv *priv = rproc->priv;
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phys_addr_t translated_sram_addr;
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u32 tmp;
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int ret;
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ret = clk_prepare_enable(priv->arc_pclk);
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if (ret)
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return ret;
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tmp = FIELD_PREP(AO_REMAP_REG0_REMAP_AHB_SRAM_BITS_17_14_FOR_ARM_CPU,
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priv->sram_pa >> 14);
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writel(tmp, priv->remap_base + AO_REMAP_REG0);
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/*
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* The SRAM content as seen by the ARC core always starts at 0x0
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* regardless of the value given here (this was discovered by trial and
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* error). For SoCs older than Meson6 we probably have to set
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* AO_REMAP_REG1_MOVE_AHB_SRAM_TO_0X0_INSTEAD_OF_DDR to achieve the
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* same. (At least) For Meson8 and newer that bit must not be set.
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*/
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writel(0x0, priv->remap_base + AO_REMAP_REG1);
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regmap_update_bits(priv->secbus2_regmap, AO_SECURE_REG0,
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AO_SECURE_REG0_AHB_SRAM_BITS_19_12,
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FIELD_PREP(AO_SECURE_REG0_AHB_SRAM_BITS_19_12,
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priv->sram_pa >> 12));
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ret = reset_control_reset(priv->arc_reset);
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if (ret) {
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clk_disable_unprepare(priv->arc_pclk);
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return ret;
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}
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usleep_range(10, 100);
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/*
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* Convert from 0xd9000000 to 0xc9000000 as the vendor driver does.
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* This only seems to be relevant for the AO_CPU_CNTL register. It is
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* unknown why this is needed.
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*/
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translated_sram_addr = priv->sram_pa - MESON_AO_RPROC_MEMORY_OFFSET;
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tmp = FIELD_PREP(AO_CPU_CNTL_AHB_SRAM_BITS_31_20,
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translated_sram_addr >> 20);
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tmp |= AO_CPU_CNTL_UNKNONWN | AO_CPU_CNTL_RUN;
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writel(tmp, priv->cpu_base + AO_CPU_CNTL);
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usleep_range(20, 200);
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return 0;
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}
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static int meson_mx_ao_arc_rproc_stop(struct rproc *rproc)
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{
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struct meson_mx_ao_arc_rproc_priv *priv = rproc->priv;
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writel(AO_CPU_CNTL_HALT, priv->cpu_base + AO_CPU_CNTL);
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clk_disable_unprepare(priv->arc_pclk);
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return 0;
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}
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static void *meson_mx_ao_arc_rproc_da_to_va(struct rproc *rproc, u64 da,
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size_t len, bool *is_iomem)
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{
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struct meson_mx_ao_arc_rproc_priv *priv = rproc->priv;
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/* The memory from the ARC core's perspective always starts at 0x0. */
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if ((da + len) > priv->sram_size)
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return NULL;
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return (void *)priv->sram_va + da;
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}
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static struct rproc_ops meson_mx_ao_arc_rproc_ops = {
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.start = meson_mx_ao_arc_rproc_start,
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.stop = meson_mx_ao_arc_rproc_stop,
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.da_to_va = meson_mx_ao_arc_rproc_da_to_va,
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.get_boot_addr = rproc_elf_get_boot_addr,
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.load = rproc_elf_load_segments,
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.sanity_check = rproc_elf_sanity_check,
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};
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static int meson_mx_ao_arc_rproc_probe(struct platform_device *pdev)
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{
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struct meson_mx_ao_arc_rproc_priv *priv;
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struct device *dev = &pdev->dev;
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const char *fw_name = NULL;
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struct rproc *rproc;
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int ret;
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device_property_read_string(dev, "firmware-name", &fw_name);
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rproc = devm_rproc_alloc(dev, "meson-mx-ao-arc",
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&meson_mx_ao_arc_rproc_ops, fw_name,
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sizeof(*priv));
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if (!rproc)
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return -ENOMEM;
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rproc->has_iommu = false;
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priv = rproc->priv;
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priv->sram_pool = of_gen_pool_get(dev->of_node, "sram", 0);
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if (!priv->sram_pool) {
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dev_err(dev, "Could not get SRAM pool\n");
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return -ENODEV;
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}
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priv->sram_size = gen_pool_avail(priv->sram_pool);
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priv->sram_va = gen_pool_alloc(priv->sram_pool, priv->sram_size);
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if (!priv->sram_va) {
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dev_err(dev, "Could not alloc memory in SRAM pool\n");
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return -ENOMEM;
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}
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priv->sram_pa = gen_pool_virt_to_phys(priv->sram_pool, priv->sram_va);
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if (priv->sram_pa & ~MESON_AO_RPROC_SRAM_USABLE_BITS) {
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dev_err(dev, "SRAM address contains unusable bits\n");
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ret = -EINVAL;
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goto err_free_genpool;
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}
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priv->secbus2_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
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"amlogic,secbus2");
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if (IS_ERR(priv->secbus2_regmap)) {
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dev_err(dev, "Failed to find SECBUS2 regmap\n");
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ret = PTR_ERR(priv->secbus2_regmap);
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goto err_free_genpool;
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}
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priv->remap_base = devm_platform_ioremap_resource_byname(pdev, "remap");
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if (IS_ERR(priv->remap_base)) {
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ret = PTR_ERR(priv->remap_base);
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goto err_free_genpool;
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}
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priv->cpu_base = devm_platform_ioremap_resource_byname(pdev, "cpu");
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if (IS_ERR(priv->cpu_base)) {
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ret = PTR_ERR(priv->cpu_base);
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goto err_free_genpool;
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}
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priv->arc_reset = devm_reset_control_get_exclusive(dev, NULL);
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if (IS_ERR(priv->arc_reset)) {
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dev_err(dev, "Failed to get ARC reset\n");
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ret = PTR_ERR(priv->arc_reset);
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goto err_free_genpool;
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}
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priv->arc_pclk = devm_clk_get(dev, NULL);
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if (IS_ERR(priv->arc_pclk)) {
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dev_err(dev, "Failed to get the ARC PCLK\n");
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ret = PTR_ERR(priv->arc_pclk);
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goto err_free_genpool;
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}
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platform_set_drvdata(pdev, rproc);
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ret = rproc_add(rproc);
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if (ret)
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goto err_free_genpool;
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return 0;
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err_free_genpool:
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gen_pool_free(priv->sram_pool, priv->sram_va, priv->sram_size);
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return ret;
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}
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static int meson_mx_ao_arc_rproc_remove(struct platform_device *pdev)
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{
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struct rproc *rproc = platform_get_drvdata(pdev);
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struct meson_mx_ao_arc_rproc_priv *priv = rproc->priv;
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rproc_del(rproc);
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gen_pool_free(priv->sram_pool, priv->sram_va, priv->sram_size);
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return 0;
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}
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static const struct of_device_id meson_mx_ao_arc_rproc_match[] = {
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{ .compatible = "amlogic,meson8-ao-arc" },
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{ .compatible = "amlogic,meson8b-ao-arc" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, meson_mx_ao_arc_rproc_match);
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static struct platform_driver meson_mx_ao_arc_rproc_driver = {
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.probe = meson_mx_ao_arc_rproc_probe,
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.remove = meson_mx_ao_arc_rproc_remove,
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.driver = {
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.name = "meson-mx-ao-arc-rproc",
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.of_match_table = meson_mx_ao_arc_rproc_match,
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},
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};
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module_platform_driver(meson_mx_ao_arc_rproc_driver);
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MODULE_DESCRIPTION("Amlogic Meson6/8/8b/8m2 AO ARC remote processor driver");
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MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
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MODULE_LICENSE("GPL v2");
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