Heiko Stübner 90c5902540 clk: rockchip: add clock type for pll clocks and pll used on rk3066 ... All known Rockchip SoCs down to the RK28xx (ARM9) use a similar pattern to handle their plls: |--\ xin32k ----------------|mux\ xin24m -----| pll |----|pll|--- pll output \---------------|src/ |--/ The pll output is sourced from 1 of 3 sources, the actual pll being one of them. To change the pll frequency it is imperative to remux it to another source beforehand. This is done by adding a clock-listener to the pll that handles the remuxing before and after the rate change. The output mux is implemented as a separate clock to make use of already existing common-clock features for disabling the pll if one of the other two sources is used. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>		2014-07-13 12:17:06 -07:00
..
clk-pll.c	clk: rockchip: add clock type for pll clocks and pll used on rk3066	2014-07-13 12:17:06 -07:00
clk-rockchip.c	clk: rockchip: fix function type for CLK_OF_DECLARE	2014-05-20 14:25:22 -05:00
clk.c	clk: rockchip: add clock type for pll clocks and pll used on rk3066	2014-07-13 12:17:06 -07:00
clk.h	clk: rockchip: add clock type for pll clocks and pll used on rk3066	2014-07-13 12:17:06 -07:00
Makefile	clk: rockchip: add clock type for pll clocks and pll used on rk3066	2014-07-13 12:17:06 -07:00