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913787ca40
spi-nor.c issues 4B commands for some Flash chips bigger than 16Mbytes. Xeon(R) D-1500 documentation mentions its Integrated PCH Logic supports Flash chips up to 64Mbytes. D-1500 Integrated PCH documenation however has inconsistencies regarding FADDR register width and says nothing about particular commands issued to support 64Mbytes of Flash. Nevetheless the tests on Xeon(R) CPU D-1548 with 512Mbit Flash chips Macronix MX25L51245G and Micron MT25QL512A showed that erase, write and read operations work just fine after SPINOR_OP_READ_4B and SPINOR_OP_READ_FAST_4B are white-listed (currently only SPINOR_OP_READ_FAST_4B is used and only for Macronix). Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> |
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| .. | ||
| aspeed-smc.c | ||
| cadence-quadspi.c | ||
| hisi-sfc.c | ||
| intel-spi-pci.c | ||
| intel-spi-platform.c | ||
| intel-spi.c | ||
| intel-spi.h | ||
| Kconfig | ||
| Makefile | ||
| mtk-quadspi.c | ||
| nxp-spifi.c | ||
| spi-nor.c | ||