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![Hans de Goede](/assets/img/avatar_default.png)
Since the sun4i irq chip does not require any action and clears the interrupt when the level goes back to inactive, we don't need to mask / unmask for non oneshot IRQs, to achieve this we make sun4i_irq_ack a nop for all irqs except irq 0 and use handle_fasteoi_irq for all interrupts. Now there might be a case when the device reactivates the interrupt before the RETI. But that does not matter as we run the primary interrupt handlers with interrupts disabled. This also allows us to get rid of needing to use 2 irq_chip structs, this means that the IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED will now influence all interrupts rather then just irq 0, but that does not matter as the eoi is now a nop anyways for all interrupts but irq 0. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-sunxi@googlegroups.com Link: http://lkml.kernel.org/r/1394895894-8891-2-git-send-email-hdegoede@redhat.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
166 lines
4.7 KiB
C
166 lines
4.7 KiB
C
/*
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* Allwinner A1X SoCs IRQ chip driver.
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*
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* Copyright (C) 2012 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* Based on code from
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Benn Huang <benn@allwinnertech.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/exception.h>
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#include <asm/mach/irq.h>
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#include "irqchip.h"
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#define SUN4I_IRQ_VECTOR_REG 0x00
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#define SUN4I_IRQ_PROTECTION_REG 0x08
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#define SUN4I_IRQ_NMI_CTRL_REG 0x0c
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#define SUN4I_IRQ_PENDING_REG(x) (0x10 + 0x4 * x)
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#define SUN4I_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x)
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#define SUN4I_IRQ_ENABLE_REG(x) (0x40 + 0x4 * x)
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#define SUN4I_IRQ_MASK_REG(x) (0x50 + 0x4 * x)
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static void __iomem *sun4i_irq_base;
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static struct irq_domain *sun4i_irq_domain;
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static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs);
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static void sun4i_irq_ack(struct irq_data *irqd)
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{
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unsigned int irq = irqd_to_hwirq(irqd);
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unsigned int irq_off = irq % 32;
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int reg = irq / 32;
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u32 val;
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if (irq != 0)
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return; /* Only IRQ 0 / the ENMI needs to be acked */
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val = readl(sun4i_irq_base + SUN4I_IRQ_PENDING_REG(reg));
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writel(val | (1 << irq_off),
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sun4i_irq_base + SUN4I_IRQ_PENDING_REG(reg));
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}
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static void sun4i_irq_mask(struct irq_data *irqd)
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{
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unsigned int irq = irqd_to_hwirq(irqd);
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unsigned int irq_off = irq % 32;
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int reg = irq / 32;
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u32 val;
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val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
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writel(val & ~(1 << irq_off),
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sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
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}
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static void sun4i_irq_unmask(struct irq_data *irqd)
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{
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unsigned int irq = irqd_to_hwirq(irqd);
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unsigned int irq_off = irq % 32;
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int reg = irq / 32;
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u32 val;
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val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
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writel(val | (1 << irq_off),
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sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
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}
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static struct irq_chip sun4i_irq_chip = {
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.name = "sun4i_irq",
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.irq_eoi = sun4i_irq_ack,
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.irq_mask = sun4i_irq_mask,
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.irq_unmask = sun4i_irq_unmask,
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.flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED,
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};
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static int sun4i_irq_map(struct irq_domain *d, unsigned int virq,
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irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(virq, &sun4i_irq_chip, handle_fasteoi_irq);
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set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
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return 0;
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}
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static struct irq_domain_ops sun4i_irq_ops = {
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.map = sun4i_irq_map,
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.xlate = irq_domain_xlate_onecell,
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};
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static int __init sun4i_of_init(struct device_node *node,
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struct device_node *parent)
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{
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sun4i_irq_base = of_iomap(node, 0);
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if (!sun4i_irq_base)
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panic("%s: unable to map IC registers\n",
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node->full_name);
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/* Disable all interrupts */
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writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(0));
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writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(1));
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writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(2));
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/* Unmask all the interrupts, ENABLE_REG(x) is used for masking */
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writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(0));
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writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(1));
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writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(2));
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/* Clear all the pending interrupts */
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writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0));
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writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(1));
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writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(2));
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/* Enable protection mode */
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writel(0x01, sun4i_irq_base + SUN4I_IRQ_PROTECTION_REG);
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/* Configure the external interrupt source type */
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writel(0x00, sun4i_irq_base + SUN4I_IRQ_NMI_CTRL_REG);
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sun4i_irq_domain = irq_domain_add_linear(node, 3 * 32,
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&sun4i_irq_ops, NULL);
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if (!sun4i_irq_domain)
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panic("%s: unable to create IRQ domain\n", node->full_name);
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set_handle_irq(sun4i_handle_irq);
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return 0;
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}
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IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_of_init);
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static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs)
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{
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u32 irq, hwirq;
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/*
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* hwirq == 0 can mean one of 3 things:
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* 1) no more irqs pending
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* 2) irq 0 pending
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* 3) spurious irq
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* So if we immediately get a reading of 0, check the irq-pending reg
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* to differentiate between 2 and 3. We only do this once to avoid
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* the extra check in the common case of 1 hapening after having
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* read the vector-reg once.
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*/
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hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
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if (hwirq == 0 &&
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!(readl(sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)) & BIT(0)))
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return;
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do {
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irq = irq_find_mapping(sun4i_irq_domain, hwirq);
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handle_IRQ(irq, regs);
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hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
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} while (hwirq != 0);
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}
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