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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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316e7f901f
Intel CPUs expect the cache bitmap provided by user-space to have on a single span of 1s, whereas AMD can support bitmaps like 0xf00f. Arm's MPAM support also allows sparse bitmaps. Similarly, Intel CPUs check at least one bit set, whereas AMD CPUs are quite happy with an empty bitmap. Arm's MPAM allows an empty bitmap. To move resctrl out to /fs/, platform differences like this need to be explained. Add two resource properties arch_has_{empty,sparse}_bitmaps. Test these around the relevant parts of cbm_validate(). Merging the validate calls causes AMD to gain the min_cbm_bits test needed for Haswell, but as it always sets this value to 1, it will never match. [ bp: Massage commit message. ] Signed-off-by: James Morse <james.morse@arm.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Babu Moger <babu.moger@amd.com> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lkml.kernel.org/r/20200708163929.2783-10-james.morse@arm.com
490 lines
12 KiB
C
490 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Resource Director Technology(RDT)
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* - Cache Allocation code.
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*
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* Copyright (C) 2016 Intel Corporation
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*
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* Authors:
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* Fenghua Yu <fenghua.yu@intel.com>
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* Tony Luck <tony.luck@intel.com>
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*
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* More information about RDT be found in the Intel (R) x86 Architecture
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* Software Developer Manual June 2016, volume 3, section 17.17.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/cpu.h>
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#include <linux/kernfs.h>
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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#include "internal.h"
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/*
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* Check whether MBA bandwidth percentage value is correct. The value is
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* checked against the minimum and max bandwidth values specified by the
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* hardware. The allocated bandwidth percentage is rounded to the next
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* control step available on the hardware.
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*/
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static bool bw_validate(char *buf, unsigned long *data, struct rdt_resource *r)
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{
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unsigned long bw;
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int ret;
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/*
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* Only linear delay values is supported for current Intel SKUs.
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*/
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if (!r->membw.delay_linear && r->membw.arch_needs_linear) {
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rdt_last_cmd_puts("No support for non-linear MB domains\n");
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return false;
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}
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ret = kstrtoul(buf, 10, &bw);
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if (ret) {
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rdt_last_cmd_printf("Non-decimal digit in MB value %s\n", buf);
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return false;
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}
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if ((bw < r->membw.min_bw || bw > r->default_ctrl) &&
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!is_mba_sc(r)) {
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rdt_last_cmd_printf("MB value %ld out of range [%d,%d]\n", bw,
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r->membw.min_bw, r->default_ctrl);
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return false;
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}
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*data = roundup(bw, (unsigned long)r->membw.bw_gran);
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return true;
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}
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int parse_bw(struct rdt_parse_data *data, struct rdt_resource *r,
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struct rdt_domain *d)
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{
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unsigned long bw_val;
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if (d->have_new_ctrl) {
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rdt_last_cmd_printf("Duplicate domain %d\n", d->id);
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return -EINVAL;
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}
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if (!bw_validate(data->buf, &bw_val, r))
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return -EINVAL;
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d->new_ctrl = bw_val;
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d->have_new_ctrl = true;
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return 0;
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}
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/*
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* Check whether a cache bit mask is valid.
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* For Intel the SDM says:
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* Please note that all (and only) contiguous '1' combinations
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* are allowed (e.g. FFFFH, 0FF0H, 003CH, etc.).
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* Additionally Haswell requires at least two bits set.
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* AMD allows non-contiguous bitmasks.
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*/
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static bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r)
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{
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unsigned long first_bit, zero_bit, val;
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unsigned int cbm_len = r->cache.cbm_len;
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int ret;
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ret = kstrtoul(buf, 16, &val);
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if (ret) {
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rdt_last_cmd_printf("Non-hex character in the mask %s\n", buf);
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return false;
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}
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if ((!r->cache.arch_has_empty_bitmaps && val == 0) ||
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val > r->default_ctrl) {
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rdt_last_cmd_puts("Mask out of range\n");
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return false;
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}
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first_bit = find_first_bit(&val, cbm_len);
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zero_bit = find_next_zero_bit(&val, cbm_len, first_bit);
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/* Are non-contiguous bitmaps allowed? */
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if (!r->cache.arch_has_sparse_bitmaps &&
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(find_next_bit(&val, cbm_len, zero_bit) < cbm_len)) {
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rdt_last_cmd_printf("The mask %lx has non-consecutive 1-bits\n", val);
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return false;
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}
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if ((zero_bit - first_bit) < r->cache.min_cbm_bits) {
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rdt_last_cmd_printf("Need at least %d bits in the mask\n",
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r->cache.min_cbm_bits);
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return false;
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}
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*data = val;
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return true;
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}
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/*
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* Read one cache bit mask (hex). Check that it is valid for the current
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* resource type.
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*/
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int parse_cbm(struct rdt_parse_data *data, struct rdt_resource *r,
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struct rdt_domain *d)
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{
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struct rdtgroup *rdtgrp = data->rdtgrp;
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u32 cbm_val;
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if (d->have_new_ctrl) {
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rdt_last_cmd_printf("Duplicate domain %d\n", d->id);
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return -EINVAL;
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}
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/*
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* Cannot set up more than one pseudo-locked region in a cache
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* hierarchy.
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*/
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if (rdtgrp->mode == RDT_MODE_PSEUDO_LOCKSETUP &&
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rdtgroup_pseudo_locked_in_hierarchy(d)) {
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rdt_last_cmd_puts("Pseudo-locked region in hierarchy\n");
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return -EINVAL;
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}
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if (!cbm_validate(data->buf, &cbm_val, r))
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return -EINVAL;
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if ((rdtgrp->mode == RDT_MODE_EXCLUSIVE ||
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rdtgrp->mode == RDT_MODE_SHAREABLE) &&
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rdtgroup_cbm_overlaps_pseudo_locked(d, cbm_val)) {
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rdt_last_cmd_puts("CBM overlaps with pseudo-locked region\n");
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return -EINVAL;
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}
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/*
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* The CBM may not overlap with the CBM of another closid if
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* either is exclusive.
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*/
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if (rdtgroup_cbm_overlaps(r, d, cbm_val, rdtgrp->closid, true)) {
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rdt_last_cmd_puts("Overlaps with exclusive group\n");
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return -EINVAL;
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}
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if (rdtgroup_cbm_overlaps(r, d, cbm_val, rdtgrp->closid, false)) {
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if (rdtgrp->mode == RDT_MODE_EXCLUSIVE ||
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rdtgrp->mode == RDT_MODE_PSEUDO_LOCKSETUP) {
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rdt_last_cmd_puts("Overlaps with other group\n");
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return -EINVAL;
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}
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}
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d->new_ctrl = cbm_val;
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d->have_new_ctrl = true;
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return 0;
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}
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/*
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* For each domain in this resource we expect to find a series of:
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* id=mask
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* separated by ";". The "id" is in decimal, and must match one of
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* the "id"s for this resource.
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*/
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static int parse_line(char *line, struct rdt_resource *r,
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struct rdtgroup *rdtgrp)
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{
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struct rdt_parse_data data;
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char *dom = NULL, *id;
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struct rdt_domain *d;
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unsigned long dom_id;
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if (rdtgrp->mode == RDT_MODE_PSEUDO_LOCKSETUP &&
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r->rid == RDT_RESOURCE_MBA) {
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rdt_last_cmd_puts("Cannot pseudo-lock MBA resource\n");
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return -EINVAL;
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}
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next:
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if (!line || line[0] == '\0')
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return 0;
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dom = strsep(&line, ";");
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id = strsep(&dom, "=");
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if (!dom || kstrtoul(id, 10, &dom_id)) {
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rdt_last_cmd_puts("Missing '=' or non-numeric domain\n");
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return -EINVAL;
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}
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dom = strim(dom);
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list_for_each_entry(d, &r->domains, list) {
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if (d->id == dom_id) {
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data.buf = dom;
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data.rdtgrp = rdtgrp;
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if (r->parse_ctrlval(&data, r, d))
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return -EINVAL;
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if (rdtgrp->mode == RDT_MODE_PSEUDO_LOCKSETUP) {
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/*
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* In pseudo-locking setup mode and just
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* parsed a valid CBM that should be
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* pseudo-locked. Only one locked region per
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* resource group and domain so just do
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* the required initialization for single
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* region and return.
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*/
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rdtgrp->plr->r = r;
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rdtgrp->plr->d = d;
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rdtgrp->plr->cbm = d->new_ctrl;
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d->plr = rdtgrp->plr;
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return 0;
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}
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goto next;
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}
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}
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return -EINVAL;
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}
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int update_domains(struct rdt_resource *r, int closid)
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{
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struct msr_param msr_param;
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cpumask_var_t cpu_mask;
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struct rdt_domain *d;
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bool mba_sc;
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u32 *dc;
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int cpu;
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if (!zalloc_cpumask_var(&cpu_mask, GFP_KERNEL))
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return -ENOMEM;
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msr_param.low = closid;
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msr_param.high = msr_param.low + 1;
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msr_param.res = r;
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mba_sc = is_mba_sc(r);
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list_for_each_entry(d, &r->domains, list) {
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dc = !mba_sc ? d->ctrl_val : d->mbps_val;
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if (d->have_new_ctrl && d->new_ctrl != dc[closid]) {
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cpumask_set_cpu(cpumask_any(&d->cpu_mask), cpu_mask);
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dc[closid] = d->new_ctrl;
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}
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}
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/*
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* Avoid writing the control msr with control values when
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* MBA software controller is enabled
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*/
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if (cpumask_empty(cpu_mask) || mba_sc)
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goto done;
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cpu = get_cpu();
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/* Update resource control msr on this CPU if it's in cpu_mask. */
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if (cpumask_test_cpu(cpu, cpu_mask))
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rdt_ctrl_update(&msr_param);
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/* Update resource control msr on other CPUs. */
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smp_call_function_many(cpu_mask, rdt_ctrl_update, &msr_param, 1);
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put_cpu();
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done:
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free_cpumask_var(cpu_mask);
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return 0;
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}
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static int rdtgroup_parse_resource(char *resname, char *tok,
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struct rdtgroup *rdtgrp)
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{
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struct rdt_resource *r;
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for_each_alloc_enabled_rdt_resource(r) {
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if (!strcmp(resname, r->name) && rdtgrp->closid < r->num_closid)
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return parse_line(tok, r, rdtgrp);
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}
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rdt_last_cmd_printf("Unknown or unsupported resource name '%s'\n", resname);
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return -EINVAL;
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}
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ssize_t rdtgroup_schemata_write(struct kernfs_open_file *of,
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char *buf, size_t nbytes, loff_t off)
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{
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struct rdtgroup *rdtgrp;
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struct rdt_domain *dom;
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struct rdt_resource *r;
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char *tok, *resname;
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int ret = 0;
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/* Valid input requires a trailing newline */
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if (nbytes == 0 || buf[nbytes - 1] != '\n')
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return -EINVAL;
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buf[nbytes - 1] = '\0';
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cpus_read_lock();
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rdtgrp = rdtgroup_kn_lock_live(of->kn);
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if (!rdtgrp) {
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rdtgroup_kn_unlock(of->kn);
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cpus_read_unlock();
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return -ENOENT;
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}
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rdt_last_cmd_clear();
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/*
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* No changes to pseudo-locked region allowed. It has to be removed
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* and re-created instead.
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*/
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if (rdtgrp->mode == RDT_MODE_PSEUDO_LOCKED) {
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ret = -EINVAL;
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rdt_last_cmd_puts("Resource group is pseudo-locked\n");
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goto out;
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}
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for_each_alloc_enabled_rdt_resource(r) {
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list_for_each_entry(dom, &r->domains, list)
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dom->have_new_ctrl = false;
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}
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while ((tok = strsep(&buf, "\n")) != NULL) {
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resname = strim(strsep(&tok, ":"));
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if (!tok) {
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rdt_last_cmd_puts("Missing ':'\n");
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ret = -EINVAL;
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goto out;
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}
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if (tok[0] == '\0') {
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rdt_last_cmd_printf("Missing '%s' value\n", resname);
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ret = -EINVAL;
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goto out;
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}
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ret = rdtgroup_parse_resource(resname, tok, rdtgrp);
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if (ret)
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goto out;
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}
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for_each_alloc_enabled_rdt_resource(r) {
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ret = update_domains(r, rdtgrp->closid);
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if (ret)
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goto out;
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}
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if (rdtgrp->mode == RDT_MODE_PSEUDO_LOCKSETUP) {
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/*
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* If pseudo-locking fails we keep the resource group in
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* mode RDT_MODE_PSEUDO_LOCKSETUP with its class of service
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* active and updated for just the domain the pseudo-locked
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* region was requested for.
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*/
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ret = rdtgroup_pseudo_lock_create(rdtgrp);
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}
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out:
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rdtgroup_kn_unlock(of->kn);
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cpus_read_unlock();
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return ret ?: nbytes;
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}
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static void show_doms(struct seq_file *s, struct rdt_resource *r, int closid)
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{
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struct rdt_domain *dom;
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bool sep = false;
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u32 ctrl_val;
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seq_printf(s, "%*s:", max_name_width, r->name);
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list_for_each_entry(dom, &r->domains, list) {
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if (sep)
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seq_puts(s, ";");
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ctrl_val = (!is_mba_sc(r) ? dom->ctrl_val[closid] :
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dom->mbps_val[closid]);
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seq_printf(s, r->format_str, dom->id, max_data_width,
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ctrl_val);
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sep = true;
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}
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seq_puts(s, "\n");
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}
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int rdtgroup_schemata_show(struct kernfs_open_file *of,
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struct seq_file *s, void *v)
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{
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struct rdtgroup *rdtgrp;
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struct rdt_resource *r;
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int ret = 0;
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u32 closid;
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rdtgrp = rdtgroup_kn_lock_live(of->kn);
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if (rdtgrp) {
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if (rdtgrp->mode == RDT_MODE_PSEUDO_LOCKSETUP) {
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for_each_alloc_enabled_rdt_resource(r)
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seq_printf(s, "%s:uninitialized\n", r->name);
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} else if (rdtgrp->mode == RDT_MODE_PSEUDO_LOCKED) {
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if (!rdtgrp->plr->d) {
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rdt_last_cmd_clear();
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rdt_last_cmd_puts("Cache domain offline\n");
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ret = -ENODEV;
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} else {
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seq_printf(s, "%s:%d=%x\n",
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rdtgrp->plr->r->name,
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rdtgrp->plr->d->id,
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rdtgrp->plr->cbm);
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}
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} else {
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closid = rdtgrp->closid;
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for_each_alloc_enabled_rdt_resource(r) {
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if (closid < r->num_closid)
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show_doms(s, r, closid);
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}
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}
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} else {
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ret = -ENOENT;
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}
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rdtgroup_kn_unlock(of->kn);
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return ret;
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}
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void mon_event_read(struct rmid_read *rr, struct rdt_resource *r,
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struct rdt_domain *d, struct rdtgroup *rdtgrp,
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int evtid, int first)
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{
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/*
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* setup the parameters to send to the IPI to read the data.
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*/
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rr->rgrp = rdtgrp;
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rr->evtid = evtid;
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rr->r = r;
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rr->d = d;
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rr->val = 0;
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rr->first = first;
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smp_call_function_any(&d->cpu_mask, mon_event_count, rr, 1);
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}
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int rdtgroup_mondata_show(struct seq_file *m, void *arg)
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{
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struct kernfs_open_file *of = m->private;
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u32 resid, evtid, domid;
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struct rdtgroup *rdtgrp;
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struct rdt_resource *r;
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union mon_data_bits md;
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struct rdt_domain *d;
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struct rmid_read rr;
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int ret = 0;
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rdtgrp = rdtgroup_kn_lock_live(of->kn);
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if (!rdtgrp) {
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ret = -ENOENT;
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goto out;
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}
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md.priv = of->kn->priv;
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resid = md.u.rid;
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domid = md.u.domid;
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evtid = md.u.evtid;
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r = &rdt_resources_all[resid];
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d = rdt_find_domain(r, domid, NULL);
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if (IS_ERR_OR_NULL(d)) {
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ret = -ENOENT;
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goto out;
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}
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mon_event_read(&rr, r, d, rdtgrp, evtid, false);
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if (rr.val & RMID_VAL_ERROR)
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seq_puts(m, "Error\n");
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else if (rr.val & RMID_VAL_UNAVAIL)
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seq_puts(m, "Unavailable\n");
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else
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seq_printf(m, "%llu\n", rr.val * r->mon_scale);
|
|
|
|
out:
|
|
rdtgroup_kn_unlock(of->kn);
|
|
return ret;
|
|
}
|