714 lines
27 KiB
ReStructuredText
714 lines
27 KiB
ReStructuredText
.. contents::
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.. sectnum::
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======================================
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BPF Instruction Set Architecture (ISA)
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======================================
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This document specifies the BPF instruction set architecture (ISA).
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Documentation conventions
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=========================
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For brevity and consistency, this document refers to families
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of types using a shorthand syntax and refers to several expository,
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mnemonic functions when describing the semantics of instructions.
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The range of valid values for those types and the semantics of those
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functions are defined in the following subsections.
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Types
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-----
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This document refers to integer types with the notation `SN` to specify
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a type's signedness (`S`) and bit width (`N`), respectively.
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.. table:: Meaning of signedness notation.
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==== =========
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S Meaning
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==== =========
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u unsigned
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s signed
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==== =========
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.. table:: Meaning of bit-width notation.
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===== =========
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N Bit width
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===== =========
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8 8 bits
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16 16 bits
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32 32 bits
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64 64 bits
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128 128 bits
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===== =========
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For example, `u32` is a type whose valid values are all the 32-bit unsigned
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numbers and `s16` is a types whose valid values are all the 16-bit signed
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numbers.
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Functions
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---------
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* htobe16: Takes an unsigned 16-bit number in host-endian format and
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returns the equivalent number as an unsigned 16-bit number in big-endian
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format.
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* htobe32: Takes an unsigned 32-bit number in host-endian format and
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returns the equivalent number as an unsigned 32-bit number in big-endian
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format.
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* htobe64: Takes an unsigned 64-bit number in host-endian format and
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returns the equivalent number as an unsigned 64-bit number in big-endian
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format.
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* htole16: Takes an unsigned 16-bit number in host-endian format and
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returns the equivalent number as an unsigned 16-bit number in little-endian
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format.
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* htole32: Takes an unsigned 32-bit number in host-endian format and
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returns the equivalent number as an unsigned 32-bit number in little-endian
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format.
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* htole64: Takes an unsigned 64-bit number in host-endian format and
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returns the equivalent number as an unsigned 64-bit number in little-endian
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format.
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* bswap16: Takes an unsigned 16-bit number in either big- or little-endian
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format and returns the equivalent number with the same bit width but
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opposite endianness.
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* bswap32: Takes an unsigned 32-bit number in either big- or little-endian
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format and returns the equivalent number with the same bit width but
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opposite endianness.
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* bswap64: Takes an unsigned 64-bit number in either big- or little-endian
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format and returns the equivalent number with the same bit width but
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opposite endianness.
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Definitions
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-----------
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.. glossary::
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Sign Extend
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To `sign extend an` ``X`` `-bit number, A, to a` ``Y`` `-bit number, B ,` means to
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#. Copy all ``X`` bits from `A` to the lower ``X`` bits of `B`.
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#. Set the value of the remaining ``Y`` - ``X`` bits of `B` to the value of
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the most-significant bit of `A`.
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.. admonition:: Example
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Sign extend an 8-bit number ``A`` to a 16-bit number ``B`` on a big-endian platform:
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::
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A: 10000110
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B: 11111111 10000110
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Conformance groups
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------------------
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An implementation does not need to support all instructions specified in this
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document (e.g., deprecated instructions). Instead, a number of conformance
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groups are specified. An implementation must support the base32 conformance
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group and may support additional conformance groups, where supporting a
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conformance group means it must support all instructions in that conformance
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group.
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The use of named conformance groups enables interoperability between a runtime
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that executes instructions, and tools as such compilers that generate
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instructions for the runtime. Thus, capability discovery in terms of
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conformance groups might be done manually by users or automatically by tools.
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Each conformance group has a short ASCII label (e.g., "base32") that
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corresponds to a set of instructions that are mandatory. That is, each
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instruction has one or more conformance groups of which it is a member.
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This document defines the following conformance groups:
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* base32: includes all instructions defined in this
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specification unless otherwise noted.
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* base64: includes base32, plus instructions explicitly noted
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as being in the base64 conformance group.
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* atomic32: includes 32-bit atomic operation instructions (see `Atomic operations`_).
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* atomic64: includes atomic32, plus 64-bit atomic operation instructions.
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* divmul32: includes 32-bit division, multiplication, and modulo instructions.
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* divmul64: includes divmul32, plus 64-bit division, multiplication,
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and modulo instructions.
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* packet: deprecated packet access instructions.
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Instruction encoding
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====================
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BPF has two instruction encodings:
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* the basic instruction encoding, which uses 64 bits to encode an instruction
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* the wide instruction encoding, which appends a second 64 bits
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after the basic instruction for a total of 128 bits.
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Basic instruction encoding
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--------------------------
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A basic instruction is encoded as follows::
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| opcode | regs | offset |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| imm |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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**opcode**
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operation to perform, encoded as follows::
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+-+-+-+-+-+-+-+-+
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|specific |class|
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+-+-+-+-+-+-+-+-+
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**specific**
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The format of these bits varies by instruction class
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**class**
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The instruction class (see `Instruction classes`_)
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**regs**
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The source and destination register numbers, encoded as follows
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on a little-endian host::
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+-+-+-+-+-+-+-+-+
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|src_reg|dst_reg|
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+-+-+-+-+-+-+-+-+
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and as follows on a big-endian host::
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+-+-+-+-+-+-+-+-+
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|dst_reg|src_reg|
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+-+-+-+-+-+-+-+-+
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**src_reg**
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the source register number (0-10), except where otherwise specified
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(`64-bit immediate instructions`_ reuse this field for other purposes)
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**dst_reg**
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destination register number (0-10)
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**offset**
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signed integer offset used with pointer arithmetic
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**imm**
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signed integer immediate value
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Note that the contents of multi-byte fields ('offset' and 'imm') are
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stored using big-endian byte ordering on big-endian hosts and
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little-endian byte ordering on little-endian hosts.
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For example::
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opcode offset imm assembly
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src_reg dst_reg
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07 0 1 00 00 44 33 22 11 r1 += 0x11223344 // little
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dst_reg src_reg
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07 1 0 00 00 11 22 33 44 r1 += 0x11223344 // big
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Note that most instructions do not use all of the fields.
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Unused fields shall be cleared to zero.
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Wide instruction encoding
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--------------------------
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Some instructions are defined to use the wide instruction encoding,
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which uses two 32-bit immediate values. The 64 bits following
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the basic instruction format contain a pseudo instruction
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with 'opcode', 'dst_reg', 'src_reg', and 'offset' all set to zero.
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This is depicted in the following figure::
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| opcode | regs | offset |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| imm |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| reserved |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| next_imm |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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**opcode**
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operation to perform, encoded as explained above
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**regs**
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The source and destination register numbers, encoded as explained above
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**offset**
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signed integer offset used with pointer arithmetic
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**imm**
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signed integer immediate value
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**reserved**
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unused, set to zero
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**next_imm**
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second signed integer immediate value
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Instruction classes
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-------------------
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The three least significant bits of the 'opcode' field store the instruction class:
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===== ===== =============================== ===================================
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class value description reference
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===== ===== =============================== ===================================
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LD 0x0 non-standard load operations `Load and store instructions`_
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LDX 0x1 load into register operations `Load and store instructions`_
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ST 0x2 store from immediate operations `Load and store instructions`_
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STX 0x3 store from register operations `Load and store instructions`_
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ALU 0x4 32-bit arithmetic operations `Arithmetic and jump instructions`_
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JMP 0x5 64-bit jump operations `Arithmetic and jump instructions`_
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JMP32 0x6 32-bit jump operations `Arithmetic and jump instructions`_
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ALU64 0x7 64-bit arithmetic operations `Arithmetic and jump instructions`_
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===== ===== =============================== ===================================
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Arithmetic and jump instructions
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================================
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For arithmetic and jump instructions (``ALU``, ``ALU64``, ``JMP`` and
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``JMP32``), the 8-bit 'opcode' field is divided into three parts::
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+-+-+-+-+-+-+-+-+
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| code |s|class|
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+-+-+-+-+-+-+-+-+
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**code**
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the operation code, whose meaning varies by instruction class
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**s (source)**
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the source operand location, which unless otherwise specified is one of:
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====== ===== ==============================================
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source value description
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====== ===== ==============================================
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K 0 use 32-bit 'imm' value as source operand
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X 1 use 'src_reg' register value as source operand
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====== ===== ==============================================
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**instruction class**
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the instruction class (see `Instruction classes`_)
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Arithmetic instructions
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-----------------------
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``ALU`` uses 32-bit wide operands while ``ALU64`` uses 64-bit wide operands for
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otherwise identical operations. ``ALU64`` instructions belong to the
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base64 conformance group unless noted otherwise.
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The 'code' field encodes the operation as below, where 'src' and 'dst' refer
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to the values of the source and destination registers, respectively.
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===== ===== ======= ==========================================================
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name code offset description
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===== ===== ======= ==========================================================
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ADD 0x0 0 dst += src
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SUB 0x1 0 dst -= src
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MUL 0x2 0 dst \*= src
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DIV 0x3 0 dst = (src != 0) ? (dst / src) : 0
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SDIV 0x3 1 dst = (src != 0) ? (dst s/ src) : 0
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OR 0x4 0 dst \|= src
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AND 0x5 0 dst &= src
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LSH 0x6 0 dst <<= (src & mask)
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RSH 0x7 0 dst >>= (src & mask)
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NEG 0x8 0 dst = -dst
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MOD 0x9 0 dst = (src != 0) ? (dst % src) : dst
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SMOD 0x9 1 dst = (src != 0) ? (dst s% src) : dst
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XOR 0xa 0 dst ^= src
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MOV 0xb 0 dst = src
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MOVSX 0xb 8/16/32 dst = (s8,s16,s32)src
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ARSH 0xc 0 :term:`sign extending<Sign Extend>` dst >>= (src & mask)
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END 0xd 0 byte swap operations (see `Byte swap instructions`_ below)
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===== ===== ======= ==========================================================
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Underflow and overflow are allowed during arithmetic operations, meaning
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the 64-bit or 32-bit value will wrap. If BPF program execution would
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result in division by zero, the destination register is instead set to zero.
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If execution would result in modulo by zero, for ``ALU64`` the value of
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the destination register is unchanged whereas for ``ALU`` the upper
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32 bits of the destination register are zeroed.
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``{ADD, X, ALU}``, where 'code' = ``ADD``, 'source' = ``X``, and 'class' = ``ALU``, means::
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dst = (u32) ((u32) dst + (u32) src)
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where '(u32)' indicates that the upper 32 bits are zeroed.
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``{ADD, X, ALU64}`` means::
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dst = dst + src
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``{XOR, K, ALU}`` means::
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dst = (u32) dst ^ (u32) imm
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``{XOR, K, ALU64}`` means::
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dst = dst ^ imm
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Note that most instructions have instruction offset of 0. Only three instructions
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(``SDIV``, ``SMOD``, ``MOVSX``) have a non-zero offset.
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Division, multiplication, and modulo operations for ``ALU`` are part
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of the "divmul32" conformance group, and division, multiplication, and
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modulo operations for ``ALU64`` are part of the "divmul64" conformance
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group.
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The division and modulo operations support both unsigned and signed flavors.
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For unsigned operations (``DIV`` and ``MOD``), for ``ALU``,
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'imm' is interpreted as a 32-bit unsigned value. For ``ALU64``,
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'imm' is first :term:`sign extended<Sign Extend>` from 32 to 64 bits, and then
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interpreted as a 64-bit unsigned value.
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For signed operations (``SDIV`` and ``SMOD``), for ``ALU``,
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'imm' is interpreted as a 32-bit signed value. For ``ALU64``, 'imm'
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is first :term:`sign extended<Sign Extend>` from 32 to 64 bits, and then
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interpreted as a 64-bit signed value.
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Note that there are varying definitions of the signed modulo operation
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when the dividend or divisor are negative, where implementations often
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vary by language such that Python, Ruby, etc. differ from C, Go, Java,
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etc. This specification requires that signed modulo use truncated division
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(where -13 % 3 == -1) as implemented in C, Go, etc.:
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a % n = a - n * trunc(a / n)
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The ``MOVSX`` instruction does a move operation with sign extension.
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``{MOVSX, X, ALU}`` :term:`sign extends<Sign Extend>` 8-bit and 16-bit operands into 32
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bit operands, and zeroes the remaining upper 32 bits.
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``{MOVSX, X, ALU64}`` :term:`sign extends<Sign Extend>` 8-bit, 16-bit, and 32-bit
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operands into 64 bit operands. Unlike other arithmetic instructions,
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``MOVSX`` is only defined for register source operands (``X``).
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The ``NEG`` instruction is only defined when the source bit is clear
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(``K``).
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Shift operations use a mask of 0x3F (63) for 64-bit operations and 0x1F (31)
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for 32-bit operations.
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Byte swap instructions
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----------------------
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The byte swap instructions use instruction classes of ``ALU`` and ``ALU64``
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and a 4-bit 'code' field of ``END``.
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The byte swap instructions operate on the destination register
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only and do not use a separate source register or immediate value.
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For ``ALU``, the 1-bit source operand field in the opcode is used to
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select what byte order the operation converts from or to. For
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``ALU64``, the 1-bit source operand field in the opcode is reserved
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and must be set to 0.
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===== ======== ===== =================================================
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class source value description
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===== ======== ===== =================================================
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ALU TO_LE 0 convert between host byte order and little endian
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ALU TO_BE 1 convert between host byte order and big endian
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ALU64 Reserved 0 do byte swap unconditionally
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===== ======== ===== =================================================
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The 'imm' field encodes the width of the swap operations. The following widths
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are supported: 16, 32 and 64. Width 64 operations belong to the base64
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conformance group and other swap operations belong to the base32
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conformance group.
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Examples:
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``{END, TO_LE, ALU}`` with imm = 16/32/64 means::
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dst = htole16(dst)
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dst = htole32(dst)
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dst = htole64(dst)
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``{END, TO_BE, ALU}`` with imm = 16/32/64 means::
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dst = htobe16(dst)
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dst = htobe32(dst)
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dst = htobe64(dst)
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``{END, TO_LE, ALU64}`` with imm = 16/32/64 means::
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dst = bswap16(dst)
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dst = bswap32(dst)
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dst = bswap64(dst)
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Jump instructions
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-----------------
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``JMP32`` uses 32-bit wide operands and indicates the base32
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conformance group, while ``JMP`` uses 64-bit wide operands for
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otherwise identical operations, and indicates the base64 conformance
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group unless otherwise specified.
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The 'code' field encodes the operation as below:
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======== ===== ======= =============================== ===================================================
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code value src_reg description notes
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======== ===== ======= =============================== ===================================================
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JA 0x0 0x0 PC += offset {JA, K, JMP} only
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JA 0x0 0x0 PC += imm {JA, K, JMP32} only
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JEQ 0x1 any PC += offset if dst == src
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JGT 0x2 any PC += offset if dst > src unsigned
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JGE 0x3 any PC += offset if dst >= src unsigned
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JSET 0x4 any PC += offset if dst & src
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JNE 0x5 any PC += offset if dst != src
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JSGT 0x6 any PC += offset if dst > src signed
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JSGE 0x7 any PC += offset if dst >= src signed
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CALL 0x8 0x0 call helper function by address {CALL, K, JMP} only, see `Helper functions`_
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CALL 0x8 0x1 call PC += imm {CALL, K, JMP} only, see `Program-local functions`_
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CALL 0x8 0x2 call helper function by BTF ID {CALL, K, JMP} only, see `Helper functions`_
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EXIT 0x9 0x0 return {CALL, K, JMP} only
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JLT 0xa any PC += offset if dst < src unsigned
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JLE 0xb any PC += offset if dst <= src unsigned
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JSLT 0xc any PC += offset if dst < src signed
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JSLE 0xd any PC += offset if dst <= src signed
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======== ===== ======= =============================== ===================================================
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The BPF program needs to store the return value into register R0 before doing an
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``EXIT``.
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Example:
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``{JSGE, X, JMP32}`` means::
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if (s32)dst s>= (s32)src goto +offset
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where 's>=' indicates a signed '>=' comparison.
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``{JA, K, JMP32}`` means::
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gotol +imm
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where 'imm' means the branch offset comes from insn 'imm' field.
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Note that there are two flavors of ``JA`` instructions. The
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``JMP`` class permits a 16-bit jump offset specified by the 'offset'
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field, whereas the ``JMP32`` class permits a 32-bit jump offset
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specified by the 'imm' field. A > 16-bit conditional jump may be
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converted to a < 16-bit conditional jump plus a 32-bit unconditional
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jump.
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All ``CALL`` and ``JA`` instructions belong to the
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base32 conformance group.
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Helper functions
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~~~~~~~~~~~~~~~~
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Helper functions are a concept whereby BPF programs can call into a
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set of function calls exposed by the underlying platform.
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Historically, each helper function was identified by an address
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encoded in the imm field. The available helper functions may differ
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for each program type, but address values are unique across all program types.
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Platforms that support the BPF Type Format (BTF) support identifying
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a helper function by a BTF ID encoded in the imm field, where the BTF ID
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identifies the helper name and type.
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Program-local functions
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~~~~~~~~~~~~~~~~~~~~~~~
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Program-local functions are functions exposed by the same BPF program as the
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caller, and are referenced by offset from the call instruction, similar to
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``JA``. The offset is encoded in the imm field of the call instruction.
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A ``EXIT`` within the program-local function will return to the caller.
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Load and store instructions
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===========================
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|
For load and store instructions (``LD``, ``LDX``, ``ST``, and ``STX``), the
|
|
8-bit 'opcode' field is divided as::
|
|
|
|
+-+-+-+-+-+-+-+-+
|
|
|mode |sz |class|
|
|
+-+-+-+-+-+-+-+-+
|
|
|
|
**mode**
|
|
The mode modifier is one of:
|
|
|
|
============= ===== ==================================== =============
|
|
mode modifier value description reference
|
|
============= ===== ==================================== =============
|
|
IMM 0 64-bit immediate instructions `64-bit immediate instructions`_
|
|
ABS 1 legacy BPF packet access (absolute) `Legacy BPF Packet access instructions`_
|
|
IND 2 legacy BPF packet access (indirect) `Legacy BPF Packet access instructions`_
|
|
MEM 3 regular load and store operations `Regular load and store operations`_
|
|
MEMSX 4 sign-extension load operations `Sign-extension load operations`_
|
|
ATOMIC 6 atomic operations `Atomic operations`_
|
|
============= ===== ==================================== =============
|
|
|
|
**sz (size)**
|
|
The size modifier is one of:
|
|
|
|
==== ===== =====================
|
|
size value description
|
|
==== ===== =====================
|
|
W 0 word (4 bytes)
|
|
H 1 half word (2 bytes)
|
|
B 2 byte
|
|
DW 3 double word (8 bytes)
|
|
==== ===== =====================
|
|
|
|
Instructions using ``DW`` belong to the base64 conformance group.
|
|
|
|
**class**
|
|
The instruction class (see `Instruction classes`_)
|
|
|
|
Regular load and store operations
|
|
---------------------------------
|
|
|
|
The ``MEM`` mode modifier is used to encode regular load and store
|
|
instructions that transfer data between a register and memory.
|
|
|
|
``{MEM, <size>, STX}`` means::
|
|
|
|
*(size *) (dst + offset) = src
|
|
|
|
``{MEM, <size>, ST}`` means::
|
|
|
|
*(size *) (dst + offset) = imm
|
|
|
|
``{MEM, <size>, LDX}`` means::
|
|
|
|
dst = *(unsigned size *) (src + offset)
|
|
|
|
Where '<size>' is one of: ``B``, ``H``, ``W``, or ``DW``, and
|
|
'unsigned size' is one of: u8, u16, u32, or u64.
|
|
|
|
Sign-extension load operations
|
|
------------------------------
|
|
|
|
The ``MEMSX`` mode modifier is used to encode :term:`sign-extension<Sign Extend>` load
|
|
instructions that transfer data between a register and memory.
|
|
|
|
``{MEMSX, <size>, LDX}`` means::
|
|
|
|
dst = *(signed size *) (src + offset)
|
|
|
|
Where size is one of: ``B``, ``H``, or ``W``, and
|
|
'signed size' is one of: s8, s16, or s32.
|
|
|
|
Atomic operations
|
|
-----------------
|
|
|
|
Atomic operations are operations that operate on memory and can not be
|
|
interrupted or corrupted by other access to the same memory region
|
|
by other BPF programs or means outside of this specification.
|
|
|
|
All atomic operations supported by BPF are encoded as store operations
|
|
that use the ``ATOMIC`` mode modifier as follows:
|
|
|
|
* ``{ATOMIC, W, STX}`` for 32-bit operations, which are
|
|
part of the "atomic32" conformance group.
|
|
* ``{ATOMIC, DW, STX}`` for 64-bit operations, which are
|
|
part of the "atomic64" conformance group.
|
|
* 8-bit and 16-bit wide atomic operations are not supported.
|
|
|
|
The 'imm' field is used to encode the actual atomic operation.
|
|
Simple atomic operation use a subset of the values defined to encode
|
|
arithmetic operations in the 'imm' field to encode the atomic operation:
|
|
|
|
======== ===== ===========
|
|
imm value description
|
|
======== ===== ===========
|
|
ADD 0x00 atomic add
|
|
OR 0x40 atomic or
|
|
AND 0x50 atomic and
|
|
XOR 0xa0 atomic xor
|
|
======== ===== ===========
|
|
|
|
|
|
``{ATOMIC, W, STX}`` with 'imm' = ADD means::
|
|
|
|
*(u32 *)(dst + offset) += src
|
|
|
|
``{ATOMIC, DW, STX}`` with 'imm' = ADD means::
|
|
|
|
*(u64 *)(dst + offset) += src
|
|
|
|
In addition to the simple atomic operations, there also is a modifier and
|
|
two complex atomic operations:
|
|
|
|
=========== ================ ===========================
|
|
imm value description
|
|
=========== ================ ===========================
|
|
FETCH 0x01 modifier: return old value
|
|
XCHG 0xe0 | FETCH atomic exchange
|
|
CMPXCHG 0xf0 | FETCH atomic compare and exchange
|
|
=========== ================ ===========================
|
|
|
|
The ``FETCH`` modifier is optional for simple atomic operations, and
|
|
always set for the complex atomic operations. If the ``FETCH`` flag
|
|
is set, then the operation also overwrites ``src`` with the value that
|
|
was in memory before it was modified.
|
|
|
|
The ``XCHG`` operation atomically exchanges ``src`` with the value
|
|
addressed by ``dst + offset``.
|
|
|
|
The ``CMPXCHG`` operation atomically compares the value addressed by
|
|
``dst + offset`` with ``R0``. If they match, the value addressed by
|
|
``dst + offset`` is replaced with ``src``. In either case, the
|
|
value that was at ``dst + offset`` before the operation is zero-extended
|
|
and loaded back to ``R0``.
|
|
|
|
64-bit immediate instructions
|
|
-----------------------------
|
|
|
|
Instructions with the ``IMM`` 'mode' modifier use the wide instruction
|
|
encoding defined in `Instruction encoding`_, and use the 'src_reg' field of the
|
|
basic instruction to hold an opcode subtype.
|
|
|
|
The following table defines a set of ``{IMM, DW, LD}`` instructions
|
|
with opcode subtypes in the 'src_reg' field, using new terms such as "map"
|
|
defined further below:
|
|
|
|
======= ========================================= =========== ==============
|
|
src_reg pseudocode imm type dst type
|
|
======= ========================================= =========== ==============
|
|
0x0 dst = (next_imm << 32) | imm integer integer
|
|
0x1 dst = map_by_fd(imm) map fd map
|
|
0x2 dst = map_val(map_by_fd(imm)) + next_imm map fd data pointer
|
|
0x3 dst = var_addr(imm) variable id data pointer
|
|
0x4 dst = code_addr(imm) integer code pointer
|
|
0x5 dst = map_by_idx(imm) map index map
|
|
0x6 dst = map_val(map_by_idx(imm)) + next_imm map index data pointer
|
|
======= ========================================= =========== ==============
|
|
|
|
where
|
|
|
|
* map_by_fd(imm) means to convert a 32-bit file descriptor into an address of a map (see `Maps`_)
|
|
* map_by_idx(imm) means to convert a 32-bit index into an address of a map
|
|
* map_val(map) gets the address of the first value in a given map
|
|
* var_addr(imm) gets the address of a platform variable (see `Platform Variables`_) with a given id
|
|
* code_addr(imm) gets the address of the instruction at a specified relative offset in number of (64-bit) instructions
|
|
* the 'imm type' can be used by disassemblers for display
|
|
* the 'dst type' can be used for verification and JIT compilation purposes
|
|
|
|
Maps
|
|
~~~~
|
|
|
|
Maps are shared memory regions accessible by BPF programs on some platforms.
|
|
A map can have various semantics as defined in a separate document, and may or
|
|
may not have a single contiguous memory region, but the 'map_val(map)' is
|
|
currently only defined for maps that do have a single contiguous memory region.
|
|
|
|
Each map can have a file descriptor (fd) if supported by the platform, where
|
|
'map_by_fd(imm)' means to get the map with the specified file descriptor. Each
|
|
BPF program can also be defined to use a set of maps associated with the
|
|
program at load time, and 'map_by_idx(imm)' means to get the map with the given
|
|
index in the set associated with the BPF program containing the instruction.
|
|
|
|
Platform Variables
|
|
~~~~~~~~~~~~~~~~~~
|
|
|
|
Platform variables are memory regions, identified by integer ids, exposed by
|
|
the runtime and accessible by BPF programs on some platforms. The
|
|
'var_addr(imm)' operation means to get the address of the memory region
|
|
identified by the given id.
|
|
|
|
Legacy BPF Packet access instructions
|
|
-------------------------------------
|
|
|
|
BPF previously introduced special instructions for access to packet data that were
|
|
carried over from classic BPF. These instructions used an instruction
|
|
class of ``LD``, a size modifier of ``W``, ``H``, or ``B``, and a
|
|
mode modifier of ``ABS`` or ``IND``. The 'dst_reg' and 'offset' fields were
|
|
set to zero, and 'src_reg' was set to zero for ``ABS``. However, these
|
|
instructions are deprecated and should no longer be used. All legacy packet
|
|
access instructions belong to the "packet" conformance group.
|