231 lines
6.6 KiB
YAML
231 lines
6.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/cdns,macb.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Cadence MACB/GEM Ethernet controller
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maintainers:
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- Nicolas Ferre <nicolas.ferre@microchip.com>
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- Claudiu Beznea <claudiu.beznea@microchip.com>
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- cdns,at91rm9200-emac # Atmel at91rm9200 SoC
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- const: cdns,emac # Generic
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- items:
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- enum:
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- cdns,zynq-gem # Xilinx Zynq-7xxx SoC
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- cdns,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
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- const: cdns,gem # Generic
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deprecated: true
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- items:
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- enum:
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- xlnx,versal-gem # Xilinx Versal
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- xlnx,zynq-gem # Xilinx Zynq-7xxx SoC
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- xlnx,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
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- const: cdns,gem # Generic
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- items:
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- enum:
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- cdns,at91sam9260-macb # Atmel at91sam9 SoCs
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- cdns,sam9x60-macb # Microchip sam9x60 SoC
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- microchip,mpfs-macb # Microchip PolarFire SoC
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- const: cdns,macb # Generic
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- items:
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- enum:
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- atmel,sama5d3-macb # 10/100Mbit IP on Atmel sama5d3 SoCs
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- enum:
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- cdns,at91sam9260-macb # Atmel at91sam9 SoCs.
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- const: cdns,macb # Generic
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- enum:
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- atmel,sama5d29-gem # GEM XL IP (10/100) on Atmel sama5d29 SoCs
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- atmel,sama5d2-gem # GEM IP (10/100) on Atmel sama5d2 SoCs
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- atmel,sama5d3-gem # Gigabit IP on Atmel sama5d3 SoCs
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- atmel,sama5d4-gem # GEM IP (10/100) on Atmel sama5d4 SoCs
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- cdns,np4-macb # NP4 SoC devices
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- microchip,sama7g5-emac # Microchip SAMA7G5 ethernet interface
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- microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface
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- sifive,fu540-c000-gem # SiFive FU540-C000 SoC
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- cdns,emac # Generic
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- cdns,gem # Generic
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- cdns,macb # Generic
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- items:
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- enum:
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- microchip,sam9x7-gem # Microchip SAM9X7 gigabit ethernet interface
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- const: microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface
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reg:
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minItems: 1
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items:
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- description: Basic register set
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- description: GEMGXL Management block registers on SiFive FU540-C000 SoC
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interrupts:
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minItems: 1
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maxItems: 8
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description: One interrupt per available hardware queue
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clocks:
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minItems: 1
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maxItems: 5
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clock-names:
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minItems: 1
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items:
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- enum: [ ether_clk, hclk, pclk ]
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- enum: [ hclk, pclk ]
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- const: tx_clk
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- enum: [ rx_clk, tsu_clk ]
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- const: tsu_clk
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local-mac-address: true
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phy-mode: true
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phy-handle: true
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phys:
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maxItems: 1
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resets:
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maxItems: 1
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description:
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Recommended with ZynqMP, specify reset control for this
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controller instance with zynqmp-reset driver.
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reset-names:
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maxItems: 1
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fixed-link: true
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iommus:
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maxItems: 1
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power-domains:
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maxItems: 1
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cdns,rx-watermark:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the receive partial store and forward mode is activated,
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the receiver will only begin to forward the packet to the external
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AHB or AXI slave when enough packet data is stored in the SRAM packet buffer.
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rx-watermark corresponds to the number of SRAM buffer locations,
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that need to be filled, before the forwarding process is activated.
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Width of the SRAM is platform dependent, and can be 4, 8 or 16 bytes.
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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mdio:
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type: object
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description:
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Node containing PHY children. If this node is not present, then PHYs will
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be direct children.
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patternProperties:
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"^ethernet-phy@[0-9a-f]$":
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type: object
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$ref: ethernet-phy.yaml#
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properties:
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reset-gpios: true
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magic-packet:
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type: boolean
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description:
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Indicates that the hardware supports waking up via magic packet.
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- phy-mode
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allOf:
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- $ref: ethernet-controller.yaml#
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- if:
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not:
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properties:
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compatible:
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contains:
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const: sifive,fu540-c000-gem
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then:
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properties:
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reg:
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maxItems: 1
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unevaluatedProperties: false
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examples:
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- |
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macb0: ethernet@fffc4000 {
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compatible = "cdns,macb";
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reg = <0xfffc4000 0x4000>;
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interrupts = <21>;
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cdns,rx-watermark = <0x44>;
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phy-mode = "rmii";
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local-mac-address = [3a 0e 03 04 05 06];
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clock-names = "pclk", "hclk", "tx_clk";
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clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-phy@1 {
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reg = <0x1>;
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reset-gpios = <&pioE 6 1>;
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};
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};
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- |
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#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
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#include <dt-bindings/power/xlnx-zynqmp-power.h>
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#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
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#include <dt-bindings/phy/phy.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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gem1: ethernet@ff0c0000 {
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compatible = "xlnx,zynqmp-gem", "cdns,gem";
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interrupt-parent = <&gic>;
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interrupts = <0 59 4>, <0 59 4>;
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reg = <0x0 0xff0c0000 0x0 0x1000>;
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clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
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<&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
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<&zynqmp_clk GEM_TSU>;
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clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
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#address-cells = <1>;
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#size-cells = <0>;
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iommus = <&smmu 0x875>;
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power-domains = <&zynqmp_firmware PD_ETH_1>;
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resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
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reset-names = "gem1_rst";
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phy-mode = "sgmii";
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phys = <&psgtr 1 PHY_TYPE_SGMII 1 1>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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};
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