244 lines
6.2 KiB
YAML
244 lines
6.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: TI SoC Ethernet Switch Controller (CPSW)
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maintainers:
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- Siddharth Vadapalli <s-vadapalli@ti.com>
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- Ravi Gunasekaran <r-gunasekaran@ti.com>
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- Roger Quadros <rogerq@kernel.org>
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description:
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The 3-port switch gigabit ethernet subsystem provides ethernet packet
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communication and can be configured as an ethernet switch. It provides the
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gigabit media independent interface (GMII),reduced gigabit media
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independent interface (RGMII), reduced media independent interface (RMII),
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the management data input output (MDIO) for physical layer device (PHY)
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management.
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properties:
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compatible:
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oneOf:
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- const: ti,cpsw-switch
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- items:
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- const: ti,am335x-cpsw-switch
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- const: ti,cpsw-switch
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- items:
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- const: ti,am4372-cpsw-switch
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- const: ti,cpsw-switch
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- items:
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- const: ti,dra7-cpsw-switch
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- const: ti,cpsw-switch
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reg:
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maxItems: 1
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description:
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The physical base address and size of full the CPSW module IO range
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'#address-cells':
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const: 1
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'#size-cells':
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const: 1
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ranges: true
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clocks:
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maxItems: 1
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description: CPSW functional clock
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clock-names:
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items:
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- const: fck
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interrupts:
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items:
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- description: RX_THRESH interrupt
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- description: RX interrupt
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- description: TX interrupt
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- description: MISC interrupt
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interrupt-names:
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items:
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- const: rx_thresh
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- const: rx
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- const: tx
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- const: misc
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pinctrl-names: true
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syscon:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the system control device node which provides access to
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efuse IO range with MAC addresses
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ethernet-ports:
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type: object
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additionalProperties: false
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properties:
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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patternProperties:
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"^port@[12]$":
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type: object
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description: CPSW external ports
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$ref: ethernet-controller.yaml#
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unevaluatedProperties: false
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properties:
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reg:
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items:
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- enum: [1, 2]
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description: CPSW port number
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phys:
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maxItems: 1
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description: phandle on phy-gmii-sel PHY
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label:
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description: label associated with this port
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ti,dual-emac-pvid:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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maximum: 1024
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description:
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Specifies default PORT VID to be used to segregate
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ports. Default value - CPSW port number.
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required:
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- reg
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- phys
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cpts:
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type: object
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unevaluatedProperties: false
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description:
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The Common Platform Time Sync (CPTS) module
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properties:
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clocks:
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maxItems: 1
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description: CPTS reference clock
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clock-names:
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items:
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- const: cpts
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cpts_clock_mult:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Numerator to convert input clock ticks into ns
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cpts_clock_shift:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Denominator to convert input clock ticks into ns.
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Mult and shift will be calculated basing on CPTS rftclk frequency if
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both cpts_clock_shift and cpts_clock_mult properties are not provided.
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required:
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- clocks
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- clock-names
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patternProperties:
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"^mdio@":
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type: object
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description:
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CPSW MDIO bus.
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$ref: ti,davinci-mdio.yaml#
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required:
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- compatible
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- reg
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- ranges
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- clocks
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- clock-names
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- interrupts
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- interrupt-names
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- '#address-cells'
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- '#size-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/dra7.h>
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mac_sw: switch@0 {
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compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch";
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reg = <0x0 0x4000>;
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ranges = <0 0 0x4000>;
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clocks = <&gmac_main_clk>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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syscon = <&scm_conf>;
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interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "rx_thresh", "rx", "tx", "misc";
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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cpsw_port1: port@1 {
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reg = <1>;
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label = "port1";
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mac-address = [ 00 00 00 00 00 00 ];
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phys = <&phy_gmii_sel 1>;
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phy-handle = <ðphy0_sw>;
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phy-mode = "rgmii";
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ti,dual-emac-pvid = <1>;
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};
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cpsw_port2: port@2 {
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reg = <2>;
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label = "wan";
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mac-address = [ 00 00 00 00 00 00 ];
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phys = <&phy_gmii_sel 2>;
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phy-handle = <ðphy1_sw>;
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phy-mode = "rgmii";
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ti,dual-emac-pvid = <2>;
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};
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};
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davinci_mdio_sw: mdio@1000 {
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compatible = "ti,cpsw-mdio","ti,davinci_mdio";
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reg = <0x1000 0x100>;
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clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <0>;
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bus_freq = <1000000>;
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ethphy0_sw: ethernet-phy@0 {
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reg = <0>;
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};
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ethphy1_sw: ethernet-phy@1 {
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reg = <1>;
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};
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};
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cpts {
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clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
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clock-names = "cpts";
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};
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};
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