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116c81f427
Systems with differing CPU i-cache/d-cache line sizes can cause problems with the cache management by software when the execution is migrated from one to another. Usually, the application reads the cache size on a CPU and then uses that length to perform cache operations. However, if it gets migrated to another CPU with a smaller cache line size, things could go completely wrong. To prevent such cases, always use the smallest cache line size among the CPUs. The kernel CPU feature infrastructure already keeps track of the safe value for all CPUID registers including CTR. This patch works around the problem by : For kernel, dynamically patch the kernel to read the cache size from the system wide copy of CTR_EL0. For applications, trap read accesses to CTR_EL0 (by clearing the SCTLR.UCT) and emulate the mrs instruction to return the system wide safe value of CTR_EL0. For faster access (i.e, avoiding to lookup the system wide value of CTR_EL0 via read_system_reg), we keep track of the pointer to table entry for CTR_EL0 in the CPU feature infrastructure. Cc: Mark Rutland <mark.rutland@arm.com> Cc: Andre Przywara <andre.przywara@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
151 lines
6.8 KiB
C
151 lines
6.8 KiB
C
/*
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* Based on arch/arm/kernel/asm-offsets.c
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*
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* Copyright (C) 1995-2003 Russell King
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* 2001-2002 Keith Owens
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <linux/dma-mapping.h>
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#include <linux/kvm_host.h>
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#include <linux/suspend.h>
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#include <asm/cpufeature.h>
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#include <asm/thread_info.h>
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#include <asm/memory.h>
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#include <asm/smp_plat.h>
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#include <asm/suspend.h>
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#include <asm/vdso_datapage.h>
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#include <linux/kbuild.h>
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#include <linux/arm-smccc.h>
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int main(void)
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{
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DEFINE(TSK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
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BLANK();
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DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));
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DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count));
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DEFINE(TI_ADDR_LIMIT, offsetof(struct thread_info, addr_limit));
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DEFINE(TI_TASK, offsetof(struct thread_info, task));
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DEFINE(TI_CPU, offsetof(struct thread_info, cpu));
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BLANK();
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DEFINE(THREAD_CPU_CONTEXT, offsetof(struct task_struct, thread.cpu_context));
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BLANK();
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DEFINE(S_X0, offsetof(struct pt_regs, regs[0]));
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DEFINE(S_X1, offsetof(struct pt_regs, regs[1]));
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DEFINE(S_X2, offsetof(struct pt_regs, regs[2]));
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DEFINE(S_X3, offsetof(struct pt_regs, regs[3]));
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DEFINE(S_X4, offsetof(struct pt_regs, regs[4]));
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DEFINE(S_X5, offsetof(struct pt_regs, regs[5]));
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DEFINE(S_X6, offsetof(struct pt_regs, regs[6]));
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DEFINE(S_X7, offsetof(struct pt_regs, regs[7]));
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DEFINE(S_X8, offsetof(struct pt_regs, regs[8]));
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DEFINE(S_X10, offsetof(struct pt_regs, regs[10]));
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DEFINE(S_X12, offsetof(struct pt_regs, regs[12]));
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DEFINE(S_X14, offsetof(struct pt_regs, regs[14]));
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DEFINE(S_X16, offsetof(struct pt_regs, regs[16]));
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DEFINE(S_X18, offsetof(struct pt_regs, regs[18]));
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DEFINE(S_X20, offsetof(struct pt_regs, regs[20]));
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DEFINE(S_X22, offsetof(struct pt_regs, regs[22]));
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DEFINE(S_X24, offsetof(struct pt_regs, regs[24]));
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DEFINE(S_X26, offsetof(struct pt_regs, regs[26]));
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DEFINE(S_X28, offsetof(struct pt_regs, regs[28]));
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DEFINE(S_LR, offsetof(struct pt_regs, regs[30]));
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DEFINE(S_SP, offsetof(struct pt_regs, sp));
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#ifdef CONFIG_COMPAT
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DEFINE(S_COMPAT_SP, offsetof(struct pt_regs, compat_sp));
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#endif
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DEFINE(S_PSTATE, offsetof(struct pt_regs, pstate));
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DEFINE(S_PC, offsetof(struct pt_regs, pc));
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DEFINE(S_ORIG_X0, offsetof(struct pt_regs, orig_x0));
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DEFINE(S_SYSCALLNO, offsetof(struct pt_regs, syscallno));
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DEFINE(S_ORIG_ADDR_LIMIT, offsetof(struct pt_regs, orig_addr_limit));
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DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs));
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BLANK();
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DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id.counter));
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BLANK();
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DEFINE(VMA_VM_MM, offsetof(struct vm_area_struct, vm_mm));
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DEFINE(VMA_VM_FLAGS, offsetof(struct vm_area_struct, vm_flags));
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BLANK();
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DEFINE(VM_EXEC, VM_EXEC);
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BLANK();
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DEFINE(PAGE_SZ, PAGE_SIZE);
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BLANK();
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DEFINE(DMA_BIDIRECTIONAL, DMA_BIDIRECTIONAL);
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DEFINE(DMA_TO_DEVICE, DMA_TO_DEVICE);
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DEFINE(DMA_FROM_DEVICE, DMA_FROM_DEVICE);
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BLANK();
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DEFINE(CLOCK_REALTIME, CLOCK_REALTIME);
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DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC);
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DEFINE(CLOCK_MONOTONIC_RAW, CLOCK_MONOTONIC_RAW);
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DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
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DEFINE(CLOCK_REALTIME_COARSE, CLOCK_REALTIME_COARSE);
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DEFINE(CLOCK_MONOTONIC_COARSE,CLOCK_MONOTONIC_COARSE);
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DEFINE(CLOCK_COARSE_RES, LOW_RES_NSEC);
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DEFINE(NSEC_PER_SEC, NSEC_PER_SEC);
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BLANK();
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DEFINE(VDSO_CS_CYCLE_LAST, offsetof(struct vdso_data, cs_cycle_last));
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DEFINE(VDSO_RAW_TIME_SEC, offsetof(struct vdso_data, raw_time_sec));
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DEFINE(VDSO_RAW_TIME_NSEC, offsetof(struct vdso_data, raw_time_nsec));
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DEFINE(VDSO_XTIME_CLK_SEC, offsetof(struct vdso_data, xtime_clock_sec));
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DEFINE(VDSO_XTIME_CLK_NSEC, offsetof(struct vdso_data, xtime_clock_nsec));
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DEFINE(VDSO_XTIME_CRS_SEC, offsetof(struct vdso_data, xtime_coarse_sec));
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DEFINE(VDSO_XTIME_CRS_NSEC, offsetof(struct vdso_data, xtime_coarse_nsec));
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DEFINE(VDSO_WTM_CLK_SEC, offsetof(struct vdso_data, wtm_clock_sec));
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DEFINE(VDSO_WTM_CLK_NSEC, offsetof(struct vdso_data, wtm_clock_nsec));
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DEFINE(VDSO_TB_SEQ_COUNT, offsetof(struct vdso_data, tb_seq_count));
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DEFINE(VDSO_CS_MONO_MULT, offsetof(struct vdso_data, cs_mono_mult));
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DEFINE(VDSO_CS_RAW_MULT, offsetof(struct vdso_data, cs_raw_mult));
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DEFINE(VDSO_CS_SHIFT, offsetof(struct vdso_data, cs_shift));
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DEFINE(VDSO_TZ_MINWEST, offsetof(struct vdso_data, tz_minuteswest));
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DEFINE(VDSO_TZ_DSTTIME, offsetof(struct vdso_data, tz_dsttime));
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DEFINE(VDSO_USE_SYSCALL, offsetof(struct vdso_data, use_syscall));
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BLANK();
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DEFINE(TVAL_TV_SEC, offsetof(struct timeval, tv_sec));
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DEFINE(TVAL_TV_USEC, offsetof(struct timeval, tv_usec));
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DEFINE(TSPEC_TV_SEC, offsetof(struct timespec, tv_sec));
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DEFINE(TSPEC_TV_NSEC, offsetof(struct timespec, tv_nsec));
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BLANK();
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DEFINE(TZ_MINWEST, offsetof(struct timezone, tz_minuteswest));
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DEFINE(TZ_DSTTIME, offsetof(struct timezone, tz_dsttime));
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BLANK();
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DEFINE(CPU_BOOT_STACK, offsetof(struct secondary_data, stack));
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BLANK();
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#ifdef CONFIG_KVM_ARM_HOST
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DEFINE(VCPU_CONTEXT, offsetof(struct kvm_vcpu, arch.ctxt));
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DEFINE(CPU_GP_REGS, offsetof(struct kvm_cpu_context, gp_regs));
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DEFINE(CPU_USER_PT_REGS, offsetof(struct kvm_regs, regs));
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DEFINE(CPU_FP_REGS, offsetof(struct kvm_regs, fp_regs));
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DEFINE(VCPU_FPEXC32_EL2, offsetof(struct kvm_vcpu, arch.ctxt.sys_regs[FPEXC32_EL2]));
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DEFINE(VCPU_HOST_CONTEXT, offsetof(struct kvm_vcpu, arch.host_cpu_context));
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#endif
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#ifdef CONFIG_CPU_PM
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DEFINE(CPU_SUSPEND_SZ, sizeof(struct cpu_suspend_ctx));
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DEFINE(CPU_CTX_SP, offsetof(struct cpu_suspend_ctx, sp));
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DEFINE(MPIDR_HASH_MASK, offsetof(struct mpidr_hash, mask));
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DEFINE(MPIDR_HASH_SHIFTS, offsetof(struct mpidr_hash, shift_aff));
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DEFINE(SLEEP_STACK_DATA_SYSTEM_REGS, offsetof(struct sleep_stack_data, system_regs));
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DEFINE(SLEEP_STACK_DATA_CALLEE_REGS, offsetof(struct sleep_stack_data, callee_saved_regs));
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#endif
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DEFINE(ARM_SMCCC_RES_X0_OFFS, offsetof(struct arm_smccc_res, a0));
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DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2));
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BLANK();
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DEFINE(HIBERN_PBE_ORIG, offsetof(struct pbe, orig_address));
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DEFINE(HIBERN_PBE_ADDR, offsetof(struct pbe, address));
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DEFINE(HIBERN_PBE_NEXT, offsetof(struct pbe, next));
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DEFINE(ARM64_FTR_SYSVAL, offsetof(struct arm64_ftr_reg, sys_val));
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return 0;
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}
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