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68b3b6f177
Mark DDR clocks as critical for AT91 devices. These clocks are enabled by bootloader when initializing DDR and needs to stay enabled. Up to this patch the DDR clocks were requested from drivers/memory/atmel-sdramc.c which does only clock request and enable. There is no need to have a separate driver just for this, thus the atmel-sdramc.c will be deleted in a subsequent patch. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20221208114515.35179-2-claudiu.beznea@microchip.com
1065 lines
27 KiB
C
1065 lines
27 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/clk-provider.h>
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#include <linux/clk/at91_pmc.h>
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#include <linux/of.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include "pmc.h"
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#define MASTER_SOURCE_MAX 4
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#define PERIPHERAL_AT91RM9200 0
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#define PERIPHERAL_AT91SAM9X5 1
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#define PERIPHERAL_MAX 64
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#define PERIPHERAL_ID_MIN 2
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#define PROG_SOURCE_MAX 5
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#define PROG_ID_MAX 7
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#define SYSTEM_MAX_ID 31
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#define GCK_INDEX_DT_AUDIO_PLL 5
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static DEFINE_SPINLOCK(mck_lock);
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#ifdef CONFIG_HAVE_AT91_AUDIO_PLL
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static void __init of_sama5d2_clk_audio_pll_frac_setup(struct device_node *np)
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{
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struct clk_hw *hw;
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const char *name = np->name;
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const char *parent_name;
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struct regmap *regmap;
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struct device_node *parent_np;
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parent_np = of_get_parent(np);
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regmap = syscon_node_to_regmap(parent_np);
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of_node_put(parent_np);
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if (IS_ERR(regmap))
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return;
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parent_name = of_clk_get_parent_name(np, 0);
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hw = at91_clk_register_audio_pll_frac(regmap, name, parent_name);
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if (IS_ERR(hw))
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return;
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of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
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}
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CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_frac_setup,
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"atmel,sama5d2-clk-audio-pll-frac",
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of_sama5d2_clk_audio_pll_frac_setup);
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static void __init of_sama5d2_clk_audio_pll_pad_setup(struct device_node *np)
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{
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struct clk_hw *hw;
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const char *name = np->name;
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const char *parent_name;
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struct regmap *regmap;
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struct device_node *parent_np;
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parent_np = of_get_parent(np);
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regmap = syscon_node_to_regmap(parent_np);
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of_node_put(parent_np);
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if (IS_ERR(regmap))
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return;
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parent_name = of_clk_get_parent_name(np, 0);
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hw = at91_clk_register_audio_pll_pad(regmap, name, parent_name);
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if (IS_ERR(hw))
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return;
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of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
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}
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CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pad_setup,
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"atmel,sama5d2-clk-audio-pll-pad",
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of_sama5d2_clk_audio_pll_pad_setup);
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static void __init of_sama5d2_clk_audio_pll_pmc_setup(struct device_node *np)
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{
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struct clk_hw *hw;
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const char *name = np->name;
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const char *parent_name;
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struct regmap *regmap;
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struct device_node *parent_np;
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parent_np = of_get_parent(np);
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regmap = syscon_node_to_regmap(parent_np);
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of_node_put(parent_np);
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if (IS_ERR(regmap))
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return;
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parent_name = of_clk_get_parent_name(np, 0);
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hw = at91_clk_register_audio_pll_pmc(regmap, name, parent_name);
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if (IS_ERR(hw))
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return;
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of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
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}
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CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pmc_setup,
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"atmel,sama5d2-clk-audio-pll-pmc",
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of_sama5d2_clk_audio_pll_pmc_setup);
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#endif /* CONFIG_HAVE_AT91_AUDIO_PLL */
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static const struct clk_pcr_layout dt_pcr_layout = {
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.offset = 0x10c,
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.cmd = BIT(12),
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.pid_mask = GENMASK(5, 0),
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.div_mask = GENMASK(17, 16),
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.gckcss_mask = GENMASK(10, 8),
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};
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#ifdef CONFIG_HAVE_AT91_GENERATED_CLK
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#define GENERATED_SOURCE_MAX 6
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#define GCK_ID_I2S0 54
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#define GCK_ID_I2S1 55
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#define GCK_ID_CLASSD 59
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static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
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{
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int num;
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u32 id;
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const char *name;
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struct clk_hw *hw;
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unsigned int num_parents;
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const char *parent_names[GENERATED_SOURCE_MAX];
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struct device_node *gcknp, *parent_np;
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struct clk_range range = CLK_RANGE(0, 0);
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struct regmap *regmap;
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num_parents = of_clk_get_parent_count(np);
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if (num_parents == 0 || num_parents > GENERATED_SOURCE_MAX)
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return;
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of_clk_parent_fill(np, parent_names, num_parents);
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num = of_get_child_count(np);
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if (!num || num > PERIPHERAL_MAX)
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return;
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parent_np = of_get_parent(np);
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regmap = syscon_node_to_regmap(parent_np);
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of_node_put(parent_np);
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if (IS_ERR(regmap))
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return;
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for_each_child_of_node(np, gcknp) {
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int chg_pid = INT_MIN;
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if (of_property_read_u32(gcknp, "reg", &id))
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continue;
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if (id < PERIPHERAL_ID_MIN || id >= PERIPHERAL_MAX)
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continue;
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if (of_property_read_string(np, "clock-output-names", &name))
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name = gcknp->name;
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of_at91_get_clk_range(gcknp, "atmel,clk-output-range",
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&range);
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if (of_device_is_compatible(np, "atmel,sama5d2-clk-generated") &&
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(id == GCK_ID_I2S0 || id == GCK_ID_I2S1 ||
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id == GCK_ID_CLASSD))
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chg_pid = GCK_INDEX_DT_AUDIO_PLL;
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hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
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&dt_pcr_layout, name,
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parent_names, NULL,
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num_parents, id, &range,
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chg_pid);
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if (IS_ERR(hw))
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continue;
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of_clk_add_hw_provider(gcknp, of_clk_hw_simple_get, hw);
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}
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}
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CLK_OF_DECLARE(of_sama5d2_clk_generated_setup, "atmel,sama5d2-clk-generated",
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of_sama5d2_clk_generated_setup);
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#endif /* CONFIG_HAVE_AT91_GENERATED_CLK */
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#ifdef CONFIG_HAVE_AT91_H32MX
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static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np)
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{
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struct clk_hw *hw;
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const char *name = np->name;
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const char *parent_name;
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struct regmap *regmap;
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struct device_node *parent_np;
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parent_np = of_get_parent(np);
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regmap = syscon_node_to_regmap(parent_np);
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of_node_put(parent_np);
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if (IS_ERR(regmap))
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return;
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parent_name = of_clk_get_parent_name(np, 0);
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hw = at91_clk_register_h32mx(regmap, name, parent_name);
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if (IS_ERR(hw))
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return;
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of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
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}
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CLK_OF_DECLARE(of_sama5d4_clk_h32mx_setup, "atmel,sama5d4-clk-h32mx",
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of_sama5d4_clk_h32mx_setup);
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#endif /* CONFIG_HAVE_AT91_H32MX */
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#ifdef CONFIG_HAVE_AT91_I2S_MUX_CLK
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#define I2S_BUS_NR 2
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static void __init of_sama5d2_clk_i2s_mux_setup(struct device_node *np)
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{
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struct regmap *regmap_sfr;
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u8 bus_id;
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const char *parent_names[2];
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struct device_node *i2s_mux_np;
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struct clk_hw *hw;
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int ret;
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regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
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if (IS_ERR(regmap_sfr))
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return;
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for_each_child_of_node(np, i2s_mux_np) {
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if (of_property_read_u8(i2s_mux_np, "reg", &bus_id))
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continue;
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if (bus_id > I2S_BUS_NR)
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continue;
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ret = of_clk_parent_fill(i2s_mux_np, parent_names, 2);
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if (ret != 2)
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continue;
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hw = at91_clk_i2s_mux_register(regmap_sfr, i2s_mux_np->name,
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parent_names, 2, bus_id);
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if (IS_ERR(hw))
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continue;
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of_clk_add_hw_provider(i2s_mux_np, of_clk_hw_simple_get, hw);
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}
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}
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CLK_OF_DECLARE(sama5d2_clk_i2s_mux, "atmel,sama5d2-clk-i2s-mux",
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of_sama5d2_clk_i2s_mux_setup);
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#endif /* CONFIG_HAVE_AT91_I2S_MUX_CLK */
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static void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np)
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{
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struct clk_hw *hw;
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const char *name = np->name;
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const char *parent_name;
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struct regmap *regmap;
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bool bypass;
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struct device_node *parent_np;
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of_property_read_string(np, "clock-output-names", &name);
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bypass = of_property_read_bool(np, "atmel,osc-bypass");
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parent_name = of_clk_get_parent_name(np, 0);
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parent_np = of_get_parent(np);
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regmap = syscon_node_to_regmap(parent_np);
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of_node_put(parent_np);
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if (IS_ERR(regmap))
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return;
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hw = at91_clk_register_main_osc(regmap, name, parent_name, bypass);
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if (IS_ERR(hw))
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return;
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of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
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}
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CLK_OF_DECLARE(at91rm9200_clk_main_osc, "atmel,at91rm9200-clk-main-osc",
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of_at91rm9200_clk_main_osc_setup);
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static void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np)
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{
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struct clk_hw *hw;
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u32 frequency = 0;
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u32 accuracy = 0;
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const char *name = np->name;
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struct regmap *regmap;
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struct device_node *parent_np;
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of_property_read_string(np, "clock-output-names", &name);
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of_property_read_u32(np, "clock-frequency", &frequency);
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of_property_read_u32(np, "clock-accuracy", &accuracy);
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parent_np = of_get_parent(np);
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regmap = syscon_node_to_regmap(parent_np);
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of_node_put(parent_np);
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if (IS_ERR(regmap))
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return;
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hw = at91_clk_register_main_rc_osc(regmap, name, frequency, accuracy);
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if (IS_ERR(hw))
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return;
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of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
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}
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CLK_OF_DECLARE(at91sam9x5_clk_main_rc_osc, "atmel,at91sam9x5-clk-main-rc-osc",
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of_at91sam9x5_clk_main_rc_osc_setup);
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static void __init of_at91rm9200_clk_main_setup(struct device_node *np)
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{
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struct clk_hw *hw;
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const char *parent_name;
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const char *name = np->name;
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struct regmap *regmap;
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struct device_node *parent_np;
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parent_name = of_clk_get_parent_name(np, 0);
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of_property_read_string(np, "clock-output-names", &name);
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parent_np = of_get_parent(np);
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regmap = syscon_node_to_regmap(parent_np);
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of_node_put(parent_np);
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if (IS_ERR(regmap))
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return;
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hw = at91_clk_register_rm9200_main(regmap, name, parent_name);
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if (IS_ERR(hw))
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return;
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of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
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}
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CLK_OF_DECLARE(at91rm9200_clk_main, "atmel,at91rm9200-clk-main",
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of_at91rm9200_clk_main_setup);
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static void __init of_at91sam9x5_clk_main_setup(struct device_node *np)
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{
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struct clk_hw *hw;
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const char *parent_names[2];
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unsigned int num_parents;
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const char *name = np->name;
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struct regmap *regmap;
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struct device_node *parent_np;
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num_parents = of_clk_get_parent_count(np);
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if (num_parents == 0 || num_parents > 2)
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return;
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of_clk_parent_fill(np, parent_names, num_parents);
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parent_np = of_get_parent(np);
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regmap = syscon_node_to_regmap(parent_np);
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of_node_put(parent_np);
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if (IS_ERR(regmap))
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return;
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of_property_read_string(np, "clock-output-names", &name);
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hw = at91_clk_register_sam9x5_main(regmap, name, parent_names,
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num_parents);
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if (IS_ERR(hw))
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return;
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of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
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}
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CLK_OF_DECLARE(at91sam9x5_clk_main, "atmel,at91sam9x5-clk-main",
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of_at91sam9x5_clk_main_setup);
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static struct clk_master_characteristics * __init
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of_at91_clk_master_get_characteristics(struct device_node *np)
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{
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struct clk_master_characteristics *characteristics;
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characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
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if (!characteristics)
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return NULL;
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if (of_at91_get_clk_range(np, "atmel,clk-output-range", &characteristics->output))
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goto out_free_characteristics;
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of_property_read_u32_array(np, "atmel,clk-divisors",
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characteristics->divisors, 4);
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characteristics->have_div3_pres =
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of_property_read_bool(np, "atmel,master-clk-have-div3-pres");
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return characteristics;
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out_free_characteristics:
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kfree(characteristics);
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return NULL;
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}
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static void __init
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of_at91_clk_master_setup(struct device_node *np,
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const struct clk_master_layout *layout)
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{
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struct clk_hw *hw;
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unsigned int num_parents;
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const char *parent_names[MASTER_SOURCE_MAX];
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const char *name = np->name;
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struct clk_master_characteristics *characteristics;
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struct regmap *regmap;
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struct device_node *parent_np;
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num_parents = of_clk_get_parent_count(np);
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if (num_parents == 0 || num_parents > MASTER_SOURCE_MAX)
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return;
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of_clk_parent_fill(np, parent_names, num_parents);
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of_property_read_string(np, "clock-output-names", &name);
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characteristics = of_at91_clk_master_get_characteristics(np);
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if (!characteristics)
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return;
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parent_np = of_get_parent(np);
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regmap = syscon_node_to_regmap(parent_np);
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of_node_put(parent_np);
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if (IS_ERR(regmap))
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return;
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hw = at91_clk_register_master_pres(regmap, "masterck_pres", num_parents,
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parent_names, layout,
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characteristics, &mck_lock);
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if (IS_ERR(hw))
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goto out_free_characteristics;
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hw = at91_clk_register_master_div(regmap, name, "masterck_pres",
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layout, characteristics,
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&mck_lock, CLK_SET_RATE_GATE, 0);
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if (IS_ERR(hw))
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goto out_free_characteristics;
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of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
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return;
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out_free_characteristics:
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kfree(characteristics);
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}
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static void __init of_at91rm9200_clk_master_setup(struct device_node *np)
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{
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of_at91_clk_master_setup(np, &at91rm9200_master_layout);
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}
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CLK_OF_DECLARE(at91rm9200_clk_master, "atmel,at91rm9200-clk-master",
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of_at91rm9200_clk_master_setup);
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static void __init of_at91sam9x5_clk_master_setup(struct device_node *np)
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{
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of_at91_clk_master_setup(np, &at91sam9x5_master_layout);
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}
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CLK_OF_DECLARE(at91sam9x5_clk_master, "atmel,at91sam9x5-clk-master",
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of_at91sam9x5_clk_master_setup);
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static void __init
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of_at91_clk_periph_setup(struct device_node *np, u8 type)
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{
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int num;
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u32 id;
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struct clk_hw *hw;
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const char *parent_name;
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const char *name;
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struct device_node *periphclknp;
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struct regmap *regmap;
|
|
struct device_node *parent_np;
|
|
|
|
parent_name = of_clk_get_parent_name(np, 0);
|
|
if (!parent_name)
|
|
return;
|
|
|
|
num = of_get_child_count(np);
|
|
if (!num || num > PERIPHERAL_MAX)
|
|
return;
|
|
|
|
parent_np = of_get_parent(np);
|
|
regmap = syscon_node_to_regmap(parent_np);
|
|
of_node_put(parent_np);
|
|
if (IS_ERR(regmap))
|
|
return;
|
|
|
|
for_each_child_of_node(np, periphclknp) {
|
|
if (of_property_read_u32(periphclknp, "reg", &id))
|
|
continue;
|
|
|
|
if (id >= PERIPHERAL_MAX)
|
|
continue;
|
|
|
|
if (of_property_read_string(np, "clock-output-names", &name))
|
|
name = periphclknp->name;
|
|
|
|
if (type == PERIPHERAL_AT91RM9200) {
|
|
hw = at91_clk_register_peripheral(regmap, name,
|
|
parent_name, id);
|
|
} else {
|
|
struct clk_range range = CLK_RANGE(0, 0);
|
|
unsigned long flags = 0;
|
|
|
|
of_at91_get_clk_range(periphclknp,
|
|
"atmel,clk-output-range",
|
|
&range);
|
|
|
|
/*
|
|
* mpddr_clk feed DDR controller and is enabled by
|
|
* bootloader thus we need to keep it enabled in case
|
|
* there is no Linux consumer for it.
|
|
*/
|
|
if (!strcmp(periphclknp->name, "mpddr_clk"))
|
|
flags = CLK_IS_CRITICAL;
|
|
|
|
hw = at91_clk_register_sam9x5_peripheral(regmap,
|
|
&pmc_pcr_lock,
|
|
&dt_pcr_layout,
|
|
name,
|
|
parent_name,
|
|
id, &range,
|
|
INT_MIN,
|
|
flags);
|
|
}
|
|
|
|
if (IS_ERR(hw))
|
|
continue;
|
|
|
|
of_clk_add_hw_provider(periphclknp, of_clk_hw_simple_get, hw);
|
|
}
|
|
}
|
|
|
|
static void __init of_at91rm9200_clk_periph_setup(struct device_node *np)
|
|
{
|
|
of_at91_clk_periph_setup(np, PERIPHERAL_AT91RM9200);
|
|
}
|
|
CLK_OF_DECLARE(at91rm9200_clk_periph, "atmel,at91rm9200-clk-peripheral",
|
|
of_at91rm9200_clk_periph_setup);
|
|
|
|
static void __init of_at91sam9x5_clk_periph_setup(struct device_node *np)
|
|
{
|
|
of_at91_clk_periph_setup(np, PERIPHERAL_AT91SAM9X5);
|
|
}
|
|
CLK_OF_DECLARE(at91sam9x5_clk_periph, "atmel,at91sam9x5-clk-peripheral",
|
|
of_at91sam9x5_clk_periph_setup);
|
|
|
|
static struct clk_pll_characteristics * __init
|
|
of_at91_clk_pll_get_characteristics(struct device_node *np)
|
|
{
|
|
int i;
|
|
int offset;
|
|
u32 tmp;
|
|
int num_output;
|
|
u32 num_cells;
|
|
struct clk_range input;
|
|
struct clk_range *output;
|
|
u8 *out = NULL;
|
|
u16 *icpll = NULL;
|
|
struct clk_pll_characteristics *characteristics;
|
|
|
|
if (of_at91_get_clk_range(np, "atmel,clk-input-range", &input))
|
|
return NULL;
|
|
|
|
if (of_property_read_u32(np, "#atmel,pll-clk-output-range-cells",
|
|
&num_cells))
|
|
return NULL;
|
|
|
|
if (num_cells < 2 || num_cells > 4)
|
|
return NULL;
|
|
|
|
if (!of_get_property(np, "atmel,pll-clk-output-ranges", &tmp))
|
|
return NULL;
|
|
num_output = tmp / (sizeof(u32) * num_cells);
|
|
|
|
characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
|
|
if (!characteristics)
|
|
return NULL;
|
|
|
|
output = kcalloc(num_output, sizeof(*output), GFP_KERNEL);
|
|
if (!output)
|
|
goto out_free_characteristics;
|
|
|
|
if (num_cells > 2) {
|
|
out = kcalloc(num_output, sizeof(*out), GFP_KERNEL);
|
|
if (!out)
|
|
goto out_free_output;
|
|
}
|
|
|
|
if (num_cells > 3) {
|
|
icpll = kcalloc(num_output, sizeof(*icpll), GFP_KERNEL);
|
|
if (!icpll)
|
|
goto out_free_output;
|
|
}
|
|
|
|
for (i = 0; i < num_output; i++) {
|
|
offset = i * num_cells;
|
|
if (of_property_read_u32_index(np,
|
|
"atmel,pll-clk-output-ranges",
|
|
offset, &tmp))
|
|
goto out_free_output;
|
|
output[i].min = tmp;
|
|
if (of_property_read_u32_index(np,
|
|
"atmel,pll-clk-output-ranges",
|
|
offset + 1, &tmp))
|
|
goto out_free_output;
|
|
output[i].max = tmp;
|
|
|
|
if (num_cells == 2)
|
|
continue;
|
|
|
|
if (of_property_read_u32_index(np,
|
|
"atmel,pll-clk-output-ranges",
|
|
offset + 2, &tmp))
|
|
goto out_free_output;
|
|
out[i] = tmp;
|
|
|
|
if (num_cells == 3)
|
|
continue;
|
|
|
|
if (of_property_read_u32_index(np,
|
|
"atmel,pll-clk-output-ranges",
|
|
offset + 3, &tmp))
|
|
goto out_free_output;
|
|
icpll[i] = tmp;
|
|
}
|
|
|
|
characteristics->input = input;
|
|
characteristics->num_output = num_output;
|
|
characteristics->output = output;
|
|
characteristics->out = out;
|
|
characteristics->icpll = icpll;
|
|
return characteristics;
|
|
|
|
out_free_output:
|
|
kfree(icpll);
|
|
kfree(out);
|
|
kfree(output);
|
|
out_free_characteristics:
|
|
kfree(characteristics);
|
|
return NULL;
|
|
}
|
|
|
|
static void __init
|
|
of_at91_clk_pll_setup(struct device_node *np,
|
|
const struct clk_pll_layout *layout)
|
|
{
|
|
u32 id;
|
|
struct clk_hw *hw;
|
|
struct regmap *regmap;
|
|
const char *parent_name;
|
|
const char *name = np->name;
|
|
struct device_node *parent_np;
|
|
struct clk_pll_characteristics *characteristics;
|
|
|
|
if (of_property_read_u32(np, "reg", &id))
|
|
return;
|
|
|
|
parent_name = of_clk_get_parent_name(np, 0);
|
|
|
|
of_property_read_string(np, "clock-output-names", &name);
|
|
|
|
parent_np = of_get_parent(np);
|
|
regmap = syscon_node_to_regmap(parent_np);
|
|
of_node_put(parent_np);
|
|
if (IS_ERR(regmap))
|
|
return;
|
|
|
|
characteristics = of_at91_clk_pll_get_characteristics(np);
|
|
if (!characteristics)
|
|
return;
|
|
|
|
hw = at91_clk_register_pll(regmap, name, parent_name, id, layout,
|
|
characteristics);
|
|
if (IS_ERR(hw))
|
|
goto out_free_characteristics;
|
|
|
|
of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
|
|
return;
|
|
|
|
out_free_characteristics:
|
|
kfree(characteristics);
|
|
}
|
|
|
|
static void __init of_at91rm9200_clk_pll_setup(struct device_node *np)
|
|
{
|
|
of_at91_clk_pll_setup(np, &at91rm9200_pll_layout);
|
|
}
|
|
CLK_OF_DECLARE(at91rm9200_clk_pll, "atmel,at91rm9200-clk-pll",
|
|
of_at91rm9200_clk_pll_setup);
|
|
|
|
static void __init of_at91sam9g45_clk_pll_setup(struct device_node *np)
|
|
{
|
|
of_at91_clk_pll_setup(np, &at91sam9g45_pll_layout);
|
|
}
|
|
CLK_OF_DECLARE(at91sam9g45_clk_pll, "atmel,at91sam9g45-clk-pll",
|
|
of_at91sam9g45_clk_pll_setup);
|
|
|
|
static void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np)
|
|
{
|
|
of_at91_clk_pll_setup(np, &at91sam9g20_pllb_layout);
|
|
}
|
|
CLK_OF_DECLARE(at91sam9g20_clk_pllb, "atmel,at91sam9g20-clk-pllb",
|
|
of_at91sam9g20_clk_pllb_setup);
|
|
|
|
static void __init of_sama5d3_clk_pll_setup(struct device_node *np)
|
|
{
|
|
of_at91_clk_pll_setup(np, &sama5d3_pll_layout);
|
|
}
|
|
CLK_OF_DECLARE(sama5d3_clk_pll, "atmel,sama5d3-clk-pll",
|
|
of_sama5d3_clk_pll_setup);
|
|
|
|
static void __init
|
|
of_at91sam9x5_clk_plldiv_setup(struct device_node *np)
|
|
{
|
|
struct clk_hw *hw;
|
|
const char *parent_name;
|
|
const char *name = np->name;
|
|
struct regmap *regmap;
|
|
struct device_node *parent_np;
|
|
|
|
parent_name = of_clk_get_parent_name(np, 0);
|
|
|
|
of_property_read_string(np, "clock-output-names", &name);
|
|
|
|
parent_np = of_get_parent(np);
|
|
regmap = syscon_node_to_regmap(parent_np);
|
|
of_node_put(parent_np);
|
|
if (IS_ERR(regmap))
|
|
return;
|
|
|
|
hw = at91_clk_register_plldiv(regmap, name, parent_name);
|
|
if (IS_ERR(hw))
|
|
return;
|
|
|
|
of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
|
|
}
|
|
CLK_OF_DECLARE(at91sam9x5_clk_plldiv, "atmel,at91sam9x5-clk-plldiv",
|
|
of_at91sam9x5_clk_plldiv_setup);
|
|
|
|
static void __init
|
|
of_at91_clk_prog_setup(struct device_node *np,
|
|
const struct clk_programmable_layout *layout,
|
|
u32 *mux_table)
|
|
{
|
|
int num;
|
|
u32 id;
|
|
struct clk_hw *hw;
|
|
unsigned int num_parents;
|
|
const char *parent_names[PROG_SOURCE_MAX];
|
|
const char *name;
|
|
struct device_node *progclknp, *parent_np;
|
|
struct regmap *regmap;
|
|
|
|
num_parents = of_clk_get_parent_count(np);
|
|
if (num_parents == 0 || num_parents > PROG_SOURCE_MAX)
|
|
return;
|
|
|
|
of_clk_parent_fill(np, parent_names, num_parents);
|
|
|
|
num = of_get_child_count(np);
|
|
if (!num || num > (PROG_ID_MAX + 1))
|
|
return;
|
|
|
|
parent_np = of_get_parent(np);
|
|
regmap = syscon_node_to_regmap(parent_np);
|
|
of_node_put(parent_np);
|
|
if (IS_ERR(regmap))
|
|
return;
|
|
|
|
for_each_child_of_node(np, progclknp) {
|
|
if (of_property_read_u32(progclknp, "reg", &id))
|
|
continue;
|
|
|
|
if (of_property_read_string(np, "clock-output-names", &name))
|
|
name = progclknp->name;
|
|
|
|
hw = at91_clk_register_programmable(regmap, name,
|
|
parent_names, num_parents,
|
|
id, layout, mux_table);
|
|
if (IS_ERR(hw))
|
|
continue;
|
|
|
|
of_clk_add_hw_provider(progclknp, of_clk_hw_simple_get, hw);
|
|
}
|
|
}
|
|
|
|
static void __init of_at91rm9200_clk_prog_setup(struct device_node *np)
|
|
{
|
|
of_at91_clk_prog_setup(np, &at91rm9200_programmable_layout, NULL);
|
|
}
|
|
CLK_OF_DECLARE(at91rm9200_clk_prog, "atmel,at91rm9200-clk-programmable",
|
|
of_at91rm9200_clk_prog_setup);
|
|
|
|
static void __init of_at91sam9g45_clk_prog_setup(struct device_node *np)
|
|
{
|
|
of_at91_clk_prog_setup(np, &at91sam9g45_programmable_layout, NULL);
|
|
}
|
|
CLK_OF_DECLARE(at91sam9g45_clk_prog, "atmel,at91sam9g45-clk-programmable",
|
|
of_at91sam9g45_clk_prog_setup);
|
|
|
|
static void __init of_at91sam9x5_clk_prog_setup(struct device_node *np)
|
|
{
|
|
of_at91_clk_prog_setup(np, &at91sam9x5_programmable_layout, NULL);
|
|
}
|
|
CLK_OF_DECLARE(at91sam9x5_clk_prog, "atmel,at91sam9x5-clk-programmable",
|
|
of_at91sam9x5_clk_prog_setup);
|
|
|
|
static void __init of_at91sam9260_clk_slow_setup(struct device_node *np)
|
|
{
|
|
struct clk_hw *hw;
|
|
const char *parent_names[2];
|
|
unsigned int num_parents;
|
|
const char *name = np->name;
|
|
struct regmap *regmap;
|
|
struct device_node *parent_np;
|
|
|
|
num_parents = of_clk_get_parent_count(np);
|
|
if (num_parents != 2)
|
|
return;
|
|
|
|
of_clk_parent_fill(np, parent_names, num_parents);
|
|
parent_np = of_get_parent(np);
|
|
regmap = syscon_node_to_regmap(parent_np);
|
|
of_node_put(parent_np);
|
|
if (IS_ERR(regmap))
|
|
return;
|
|
|
|
of_property_read_string(np, "clock-output-names", &name);
|
|
|
|
hw = at91_clk_register_sam9260_slow(regmap, name, parent_names,
|
|
num_parents);
|
|
if (IS_ERR(hw))
|
|
return;
|
|
|
|
of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
|
|
}
|
|
CLK_OF_DECLARE(at91sam9260_clk_slow, "atmel,at91sam9260-clk-slow",
|
|
of_at91sam9260_clk_slow_setup);
|
|
|
|
#ifdef CONFIG_HAVE_AT91_SMD
|
|
#define SMD_SOURCE_MAX 2
|
|
|
|
static void __init of_at91sam9x5_clk_smd_setup(struct device_node *np)
|
|
{
|
|
struct clk_hw *hw;
|
|
unsigned int num_parents;
|
|
const char *parent_names[SMD_SOURCE_MAX];
|
|
const char *name = np->name;
|
|
struct regmap *regmap;
|
|
struct device_node *parent_np;
|
|
|
|
num_parents = of_clk_get_parent_count(np);
|
|
if (num_parents == 0 || num_parents > SMD_SOURCE_MAX)
|
|
return;
|
|
|
|
of_clk_parent_fill(np, parent_names, num_parents);
|
|
|
|
of_property_read_string(np, "clock-output-names", &name);
|
|
|
|
parent_np = of_get_parent(np);
|
|
regmap = syscon_node_to_regmap(parent_np);
|
|
of_node_put(parent_np);
|
|
if (IS_ERR(regmap))
|
|
return;
|
|
|
|
hw = at91sam9x5_clk_register_smd(regmap, name, parent_names,
|
|
num_parents);
|
|
if (IS_ERR(hw))
|
|
return;
|
|
|
|
of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
|
|
}
|
|
CLK_OF_DECLARE(at91sam9x5_clk_smd, "atmel,at91sam9x5-clk-smd",
|
|
of_at91sam9x5_clk_smd_setup);
|
|
#endif /* CONFIG_HAVE_AT91_SMD */
|
|
|
|
static void __init of_at91rm9200_clk_sys_setup(struct device_node *np)
|
|
{
|
|
int num;
|
|
u32 id;
|
|
struct clk_hw *hw;
|
|
const char *name;
|
|
struct device_node *sysclknp, *parent_np;
|
|
const char *parent_name;
|
|
struct regmap *regmap;
|
|
|
|
num = of_get_child_count(np);
|
|
if (num > (SYSTEM_MAX_ID + 1))
|
|
return;
|
|
|
|
parent_np = of_get_parent(np);
|
|
regmap = syscon_node_to_regmap(parent_np);
|
|
of_node_put(parent_np);
|
|
if (IS_ERR(regmap))
|
|
return;
|
|
|
|
for_each_child_of_node(np, sysclknp) {
|
|
unsigned long flags = 0;
|
|
|
|
if (of_property_read_u32(sysclknp, "reg", &id))
|
|
continue;
|
|
|
|
if (of_property_read_string(np, "clock-output-names", &name))
|
|
name = sysclknp->name;
|
|
|
|
parent_name = of_clk_get_parent_name(sysclknp, 0);
|
|
|
|
/*
|
|
* ddrck feeds DDR controller and is enabled by bootloader thus
|
|
* we need to keep it enabled in case there is no Linux consumer
|
|
* for it.
|
|
*/
|
|
if (!strcmp(sysclknp->name, "ddrck"))
|
|
flags = CLK_IS_CRITICAL;
|
|
|
|
hw = at91_clk_register_system(regmap, name, parent_name, id,
|
|
flags);
|
|
if (IS_ERR(hw))
|
|
continue;
|
|
|
|
of_clk_add_hw_provider(sysclknp, of_clk_hw_simple_get, hw);
|
|
}
|
|
}
|
|
CLK_OF_DECLARE(at91rm9200_clk_sys, "atmel,at91rm9200-clk-system",
|
|
of_at91rm9200_clk_sys_setup);
|
|
|
|
#ifdef CONFIG_HAVE_AT91_USB_CLK
|
|
#define USB_SOURCE_MAX 2
|
|
|
|
static void __init of_at91sam9x5_clk_usb_setup(struct device_node *np)
|
|
{
|
|
struct clk_hw *hw;
|
|
unsigned int num_parents;
|
|
const char *parent_names[USB_SOURCE_MAX];
|
|
const char *name = np->name;
|
|
struct regmap *regmap;
|
|
struct device_node *parent_np;
|
|
|
|
num_parents = of_clk_get_parent_count(np);
|
|
if (num_parents == 0 || num_parents > USB_SOURCE_MAX)
|
|
return;
|
|
|
|
of_clk_parent_fill(np, parent_names, num_parents);
|
|
|
|
of_property_read_string(np, "clock-output-names", &name);
|
|
|
|
parent_np = of_get_parent(np);
|
|
regmap = syscon_node_to_regmap(parent_np);
|
|
of_node_put(parent_np);
|
|
if (IS_ERR(regmap))
|
|
return;
|
|
|
|
hw = at91sam9x5_clk_register_usb(regmap, name, parent_names,
|
|
num_parents);
|
|
if (IS_ERR(hw))
|
|
return;
|
|
|
|
of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
|
|
}
|
|
CLK_OF_DECLARE(at91sam9x5_clk_usb, "atmel,at91sam9x5-clk-usb",
|
|
of_at91sam9x5_clk_usb_setup);
|
|
|
|
static void __init of_at91sam9n12_clk_usb_setup(struct device_node *np)
|
|
{
|
|
struct clk_hw *hw;
|
|
const char *parent_name;
|
|
const char *name = np->name;
|
|
struct regmap *regmap;
|
|
struct device_node *parent_np;
|
|
|
|
parent_name = of_clk_get_parent_name(np, 0);
|
|
if (!parent_name)
|
|
return;
|
|
|
|
of_property_read_string(np, "clock-output-names", &name);
|
|
|
|
parent_np = of_get_parent(np);
|
|
regmap = syscon_node_to_regmap(parent_np);
|
|
of_node_put(parent_np);
|
|
if (IS_ERR(regmap))
|
|
return;
|
|
|
|
hw = at91sam9n12_clk_register_usb(regmap, name, parent_name);
|
|
if (IS_ERR(hw))
|
|
return;
|
|
|
|
of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
|
|
}
|
|
CLK_OF_DECLARE(at91sam9n12_clk_usb, "atmel,at91sam9n12-clk-usb",
|
|
of_at91sam9n12_clk_usb_setup);
|
|
|
|
static void __init of_at91rm9200_clk_usb_setup(struct device_node *np)
|
|
{
|
|
struct clk_hw *hw;
|
|
const char *parent_name;
|
|
const char *name = np->name;
|
|
u32 divisors[4] = {0, 0, 0, 0};
|
|
struct regmap *regmap;
|
|
struct device_node *parent_np;
|
|
|
|
parent_name = of_clk_get_parent_name(np, 0);
|
|
if (!parent_name)
|
|
return;
|
|
|
|
of_property_read_u32_array(np, "atmel,clk-divisors", divisors, 4);
|
|
if (!divisors[0])
|
|
return;
|
|
|
|
of_property_read_string(np, "clock-output-names", &name);
|
|
|
|
parent_np = of_get_parent(np);
|
|
regmap = syscon_node_to_regmap(parent_np);
|
|
of_node_put(parent_np);
|
|
if (IS_ERR(regmap))
|
|
return;
|
|
hw = at91rm9200_clk_register_usb(regmap, name, parent_name, divisors);
|
|
if (IS_ERR(hw))
|
|
return;
|
|
|
|
of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
|
|
}
|
|
CLK_OF_DECLARE(at91rm9200_clk_usb, "atmel,at91rm9200-clk-usb",
|
|
of_at91rm9200_clk_usb_setup);
|
|
#endif /* CONFIG_HAVE_AT91_USB_CLK */
|
|
|
|
#ifdef CONFIG_HAVE_AT91_UTMI
|
|
static void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np)
|
|
{
|
|
struct clk_hw *hw;
|
|
const char *parent_name;
|
|
const char *name = np->name;
|
|
struct regmap *regmap_pmc, *regmap_sfr;
|
|
struct device_node *parent_np;
|
|
|
|
parent_name = of_clk_get_parent_name(np, 0);
|
|
|
|
of_property_read_string(np, "clock-output-names", &name);
|
|
|
|
parent_np = of_get_parent(np);
|
|
regmap_pmc = syscon_node_to_regmap(parent_np);
|
|
of_node_put(parent_np);
|
|
if (IS_ERR(regmap_pmc))
|
|
return;
|
|
|
|
/*
|
|
* If the device supports different mainck rates, this value has to be
|
|
* set in the UTMI Clock Trimming register.
|
|
* - 9x5: mainck supports several rates but it is indicated that a
|
|
* 12 MHz is needed in case of USB.
|
|
* - sama5d3 and sama5d2: mainck supports several rates. Configuring
|
|
* the FREQ field of the UTMI Clock Trimming register is mandatory.
|
|
* - sama5d4: mainck is at 12 MHz.
|
|
*
|
|
* We only need to retrieve sama5d3 or sama5d2 sfr regmap.
|
|
*/
|
|
regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d3-sfr");
|
|
if (IS_ERR(regmap_sfr)) {
|
|
regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
|
|
if (IS_ERR(regmap_sfr))
|
|
regmap_sfr = NULL;
|
|
}
|
|
|
|
hw = at91_clk_register_utmi(regmap_pmc, regmap_sfr, name, parent_name);
|
|
if (IS_ERR(hw))
|
|
return;
|
|
|
|
of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
|
|
}
|
|
CLK_OF_DECLARE(at91sam9x5_clk_utmi, "atmel,at91sam9x5-clk-utmi",
|
|
of_at91sam9x5_clk_utmi_setup);
|
|
#endif /* CONFIG_HAVE_AT91_UTMI */
|