Marc Zyngier 16ca6a607d KVM: arm/arm64: vgic: Don't populate multiple LRs with the same vintid ... The vgic code is trying to be clever when injecting GICv2 SGIs, and will happily populate LRs with the same interrupt number if they come from multiple vcpus (after all, they are distinct interrupt sources). Unfortunately, this is against the letter of the architecture, and the GICv2 architecture spec says "Each valid interrupt stored in the List registers must have a unique VirtualID for that virtual CPU interface.". GICv3 has similar (although slightly ambiguous) restrictions. This results in guests locking up when using GICv2-on-GICv3, for example. The obvious fix is to stop trying so hard, and inject a single vcpu per SGI per guest entry. After all, pending SGIs with multiple source vcpus are pretty rare, and are mostly seen in scenario where the physical CPUs are severely overcomitted. But as we now only inject a single instance of a multi-source SGI per vcpu entry, we may delay those interrupts for longer than strictly necessary, and run the risk of injecting lower priority interrupts in the meantime. In order to address this, we adopt a three stage strategy: - If we encounter a multi-source SGI in the AP list while computing its depth, we force the list to be sorted - When populating the LRs, we prevent the injection of any interrupt of lower priority than that of the first multi-source SGI we've injected. - Finally, the injection of a multi-source SGI triggers the request of a maintenance interrupt when there will be no pending interrupt in the LRs (HCR_NPIE). At the point where the last pending interrupt in the LRs switches from Pending to Active, the maintenance interrupt will be delivered, allowing us to add the remaining SGIs using the same process. Cc: stable@vger.kernel.org Fixes: 0919e84c0f ("KVM: arm/arm64: vgic-new: Add IRQ sync/flush framework") Acked-by: Christoffer Dall <cdall@kernel.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>		2018-03-14 18:31:04 +00:00
..
arm-gic-common.h	irqchip/gic-v3: Advertise GICv4 support to KVM	2017-08-31 15:31:42 +01:00
arm-gic-v3.h	KVM: arm/arm64: vgic: Don't populate multiple LRs with the same vintid	2018-03-14 18:31:04 +00:00
arm-gic-v4.h	irqchip/gic-v4: Add forward definition of struct irq_domain_ops	2017-11-13 16:21:33 +00:00
arm-gic.h	KVM: arm/arm64: vgic: Don't populate multiple LRs with the same vintid	2018-03-14 18:31:04 +00:00
arm-vic.h
chained_irq.h
ingenic.h
irq-bcm2836.h	irqchip: bcm2836: Move SMP startup code to arch/arm (v2)	2017-09-25 11:52:26 -07:00
irq-omap-intc.h	irqchip/irq-omap-intc: Remove omap3_init_irq()	2017-10-16 21:05:14 +02:00
irq-partition-percpu.h	irqchip: Add per-cpu interrupt partitioning library	2016-05-02 13:42:51 +02:00
irq-sa11x0.h
metag-ext.h	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
metag.h	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
mmp.h	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
mxs.h
versatile-fpga.h	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
xtensa-mx.h
xtensa-pic.h