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![Zhang Rui](/assets/img/avatar_default.png)
On Sapphire Rapids, the layout of the Psys domain Power Limit Register is different from from what it was before. Enhance the code to support the new Psys PL register layout. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reported-and-tested-by: Alkattan Dana <dana.alkattan@intel.com> [ rjw: Subject and changelog edits ] Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
163 lines
4.3 KiB
C
163 lines
4.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Data types and headers for RAPL support
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*
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* Copyright (C) 2019 Intel Corporation.
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*
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* Author: Zhang Rui <rui.zhang@intel.com>
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*/
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#ifndef __INTEL_RAPL_H__
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#define __INTEL_RAPL_H__
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#include <linux/types.h>
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#include <linux/powercap.h>
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#include <linux/cpuhotplug.h>
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enum rapl_domain_type {
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RAPL_DOMAIN_PACKAGE, /* entire package/socket */
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RAPL_DOMAIN_PP0, /* core power plane */
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RAPL_DOMAIN_PP1, /* graphics uncore */
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RAPL_DOMAIN_DRAM, /* DRAM control_type */
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RAPL_DOMAIN_PLATFORM, /* PSys control_type */
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RAPL_DOMAIN_MAX,
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};
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enum rapl_domain_reg_id {
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RAPL_DOMAIN_REG_LIMIT,
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RAPL_DOMAIN_REG_STATUS,
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RAPL_DOMAIN_REG_PERF,
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RAPL_DOMAIN_REG_POLICY,
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RAPL_DOMAIN_REG_INFO,
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RAPL_DOMAIN_REG_PL4,
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RAPL_DOMAIN_REG_MAX,
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};
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struct rapl_domain;
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enum rapl_primitives {
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ENERGY_COUNTER,
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POWER_LIMIT1,
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POWER_LIMIT2,
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POWER_LIMIT4,
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FW_LOCK,
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PL1_ENABLE, /* power limit 1, aka long term */
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PL1_CLAMP, /* allow frequency to go below OS request */
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PL2_ENABLE, /* power limit 2, aka short term, instantaneous */
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PL2_CLAMP,
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PL4_ENABLE, /* power limit 4, aka max peak power */
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TIME_WINDOW1, /* long term */
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TIME_WINDOW2, /* short term */
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THERMAL_SPEC_POWER,
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MAX_POWER,
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MIN_POWER,
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MAX_TIME_WINDOW,
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THROTTLED_TIME,
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PRIORITY_LEVEL,
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PSYS_POWER_LIMIT1,
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PSYS_POWER_LIMIT2,
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PSYS_PL1_ENABLE,
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PSYS_PL2_ENABLE,
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PSYS_TIME_WINDOW1,
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PSYS_TIME_WINDOW2,
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/* below are not raw primitive data */
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AVERAGE_POWER,
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NR_RAPL_PRIMITIVES,
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};
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struct rapl_domain_data {
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u64 primitives[NR_RAPL_PRIMITIVES];
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unsigned long timestamp;
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};
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#define NR_POWER_LIMITS (3)
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struct rapl_power_limit {
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struct powercap_zone_constraint *constraint;
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int prim_id; /* primitive ID used to enable */
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struct rapl_domain *domain;
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const char *name;
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u64 last_power_limit;
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};
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struct rapl_package;
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#define RAPL_DOMAIN_NAME_LENGTH 16
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struct rapl_domain {
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char name[RAPL_DOMAIN_NAME_LENGTH];
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enum rapl_domain_type id;
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u64 regs[RAPL_DOMAIN_REG_MAX];
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struct powercap_zone power_zone;
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struct rapl_domain_data rdd;
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struct rapl_power_limit rpl[NR_POWER_LIMITS];
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u64 attr_map; /* track capabilities */
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unsigned int state;
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unsigned int domain_energy_unit;
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struct rapl_package *rp;
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};
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struct reg_action {
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u64 reg;
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u64 mask;
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u64 value;
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int err;
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};
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/**
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* struct rapl_if_priv: private data for different RAPL interfaces
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* @control_type: Each RAPL interface must have its own powercap
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* control type.
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* @platform_rapl_domain: Optional. Some RAPL interface may have platform
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* level RAPL control.
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* @pcap_rapl_online: CPU hotplug state for each RAPL interface.
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* @reg_unit: Register for getting energy/power/time unit.
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* @regs: Register sets for different RAPL Domains.
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* @limits: Number of power limits supported by each domain.
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* @read_raw: Callback for reading RAPL interface specific
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* registers.
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* @write_raw: Callback for writing RAPL interface specific
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* registers.
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*/
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struct rapl_if_priv {
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struct powercap_control_type *control_type;
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struct rapl_domain *platform_rapl_domain;
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enum cpuhp_state pcap_rapl_online;
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u64 reg_unit;
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u64 regs[RAPL_DOMAIN_MAX][RAPL_DOMAIN_REG_MAX];
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int limits[RAPL_DOMAIN_MAX];
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int (*read_raw)(int cpu, struct reg_action *ra);
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int (*write_raw)(int cpu, struct reg_action *ra);
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};
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/* maximum rapl package domain name: package-%d-die-%d */
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#define PACKAGE_DOMAIN_NAME_LENGTH 30
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struct rapl_package {
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unsigned int id; /* logical die id, equals physical 1-die systems */
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unsigned int nr_domains;
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unsigned long domain_map; /* bit map of active domains */
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unsigned int power_unit;
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unsigned int energy_unit;
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unsigned int time_unit;
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struct rapl_domain *domains; /* array of domains, sized at runtime */
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struct powercap_zone *power_zone; /* keep track of parent zone */
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unsigned long power_limit_irq; /* keep track of package power limit
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* notify interrupt enable status.
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*/
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struct list_head plist;
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int lead_cpu; /* one active cpu per package for access */
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/* Track active cpus */
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struct cpumask cpumask;
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char name[PACKAGE_DOMAIN_NAME_LENGTH];
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struct rapl_if_priv *priv;
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};
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struct rapl_package *rapl_find_package_domain(int cpu, struct rapl_if_priv *priv);
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struct rapl_package *rapl_add_package(int cpu, struct rapl_if_priv *priv);
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void rapl_remove_package(struct rapl_package *rp);
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#endif /* __INTEL_RAPL_H__ */
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