Andy Shevchenko 934891b0a1 dmaengine: dw: Don't pollute CTL_LO on iDMA 32-bit ... Intel iDMA 32-bit doesn't have a concept of bus masters and thus there is no need to setup any kind of masters in the CTL_LO register. Moreover, the burst size for memory-to-memory transfer is not what is says, we need to have a corrected list of possible sizes. Note, that the size of 8 items, each of that up to 4 bytes, is chosen because of maximum of 1/2 FIFO, which is 64 bytes on Intel Merrifield. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>		2019-01-07 17:57:13 +05:30
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core.c	dmaengine: dw: Don't pollute CTL_LO on iDMA 32-bit	2019-01-07 17:57:13 +05:30
dw.c	dmaengine: dw: Don't pollute CTL_LO on iDMA 32-bit	2019-01-07 17:57:13 +05:30
idma32.c	dmaengine: dw: Don't pollute CTL_LO on iDMA 32-bit	2019-01-07 17:57:13 +05:30
internal.h	dmaengine: dw: Split DW and iDMA 32-bit operations	2019-01-07 17:57:13 +05:30
Kconfig	dmaengine: dw: Remove AVR32 bits from the driver	2017-05-15 17:07:30 +02:00
Makefile	dmaengine: dw: Split DW and iDMA 32-bit operations	2019-01-07 17:57:13 +05:30
pci.c	dmaengine: dw: Split DW and iDMA 32-bit operations	2019-01-07 17:57:13 +05:30
platform.c	dmaengine: dw: Split DW and iDMA 32-bit operations	2019-01-07 17:57:13 +05:30
regs.h	dmaengine: dw: Don't pollute CTL_LO on iDMA 32-bit	2019-01-07 17:57:13 +05:30