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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
249 lines
6.8 KiB
C
249 lines
6.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2011 Marvell International Ltd. All rights reserved.
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*/
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#ifndef __ASM_ARCH_REGS_USB_H
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#define __ASM_ARCH_REGS_USB_H
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#define PXA168_U2O_REGBASE (0xd4208000)
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#define PXA168_U2O_PHYBASE (0xd4207000)
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#define PXA168_U2H_REGBASE (0xd4209000)
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#define PXA168_U2H_PHYBASE (0xd4206000)
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#define MMP3_HSIC1_REGBASE (0xf0001000)
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#define MMP3_HSIC1_PHYBASE (0xf0001800)
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#define MMP3_HSIC2_REGBASE (0xf0002000)
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#define MMP3_HSIC2_PHYBASE (0xf0002800)
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#define MMP3_FSIC_REGBASE (0xf0003000)
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#define MMP3_FSIC_PHYBASE (0xf0003800)
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#define USB_REG_RANGE (0x1ff)
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#define USB_PHY_RANGE (0xff)
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/* registers */
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#define U2x_CAPREGS_OFFSET 0x100
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/* phy regs */
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#define UTMI_REVISION 0x0
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#define UTMI_CTRL 0x4
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#define UTMI_PLL 0x8
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#define UTMI_TX 0xc
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#define UTMI_RX 0x10
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#define UTMI_IVREF 0x14
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#define UTMI_T0 0x18
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#define UTMI_T1 0x1c
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#define UTMI_T2 0x20
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#define UTMI_T3 0x24
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#define UTMI_T4 0x28
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#define UTMI_T5 0x2c
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#define UTMI_RESERVE 0x30
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#define UTMI_USB_INT 0x34
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#define UTMI_DBG_CTL 0x38
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#define UTMI_OTG_ADDON 0x3c
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/* For UTMICTRL Register */
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#define UTMI_CTRL_USB_CLK_EN (1 << 31)
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/* pxa168 */
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#define UTMI_CTRL_SUSPEND_SET1 (1 << 30)
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#define UTMI_CTRL_SUSPEND_SET2 (1 << 29)
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#define UTMI_CTRL_RXBUF_PDWN (1 << 24)
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#define UTMI_CTRL_TXBUF_PDWN (1 << 11)
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#define UTMI_CTRL_INPKT_DELAY_SHIFT 30
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#define UTMI_CTRL_INPKT_DELAY_SOF_SHIFT 28
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#define UTMI_CTRL_PU_REF_SHIFT 20
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#define UTMI_CTRL_ARC_PULLDN_SHIFT 12
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#define UTMI_CTRL_PLL_PWR_UP_SHIFT 1
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#define UTMI_CTRL_PWR_UP_SHIFT 0
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/* For UTMI_PLL Register */
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#define UTMI_PLL_PLLCALI12_SHIFT 29
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#define UTMI_PLL_PLLCALI12_MASK (0x3 << 29)
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#define UTMI_PLL_PLLVDD18_SHIFT 27
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#define UTMI_PLL_PLLVDD18_MASK (0x3 << 27)
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#define UTMI_PLL_PLLVDD12_SHIFT 25
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#define UTMI_PLL_PLLVDD12_MASK (0x3 << 25)
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#define UTMI_PLL_CLK_BLK_EN_SHIFT 24
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#define CLK_BLK_EN (0x1 << 24)
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#define PLL_READY (0x1 << 23)
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#define KVCO_EXT (0x1 << 22)
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#define VCOCAL_START (0x1 << 21)
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#define UTMI_PLL_KVCO_SHIFT 15
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#define UTMI_PLL_KVCO_MASK (0x7 << 15)
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#define UTMI_PLL_ICP_SHIFT 12
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#define UTMI_PLL_ICP_MASK (0x7 << 12)
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#define UTMI_PLL_FBDIV_SHIFT 4
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#define UTMI_PLL_FBDIV_MASK (0xFF << 4)
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#define UTMI_PLL_REFDIV_SHIFT 0
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#define UTMI_PLL_REFDIV_MASK (0xF << 0)
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/* For UTMI_TX Register */
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#define UTMI_TX_REG_EXT_FS_RCAL_SHIFT 27
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#define UTMI_TX_REG_EXT_FS_RCAL_MASK (0xf << 27)
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#define UTMI_TX_REG_EXT_FS_RCAL_EN_SHIFT 26
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#define UTMI_TX_REG_EXT_FS_RCAL_EN_MASK (0x1 << 26)
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#define UTMI_TX_TXVDD12_SHIFT 22
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#define UTMI_TX_TXVDD12_MASK (0x3 << 22)
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#define UTMI_TX_CK60_PHSEL_SHIFT 17
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#define UTMI_TX_CK60_PHSEL_MASK (0xf << 17)
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#define UTMI_TX_IMPCAL_VTH_SHIFT 14
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#define UTMI_TX_IMPCAL_VTH_MASK (0x7 << 14)
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#define REG_RCAL_START (0x1 << 12)
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#define UTMI_TX_LOW_VDD_EN_SHIFT 11
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#define UTMI_TX_AMP_SHIFT 0
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#define UTMI_TX_AMP_MASK (0x7 << 0)
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/* For UTMI_RX Register */
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#define UTMI_REG_SQ_LENGTH_SHIFT 15
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#define UTMI_REG_SQ_LENGTH_MASK (0x3 << 15)
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#define UTMI_RX_SQ_THRESH_SHIFT 4
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#define UTMI_RX_SQ_THRESH_MASK (0xf << 4)
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#define UTMI_OTG_ADDON_OTG_ON (1 << 0)
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/* For MMP3 USB Phy */
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#define USB2_PLL_REG0 0x4
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#define USB2_PLL_REG1 0x8
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#define USB2_TX_REG0 0x10
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#define USB2_TX_REG1 0x14
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#define USB2_TX_REG2 0x18
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#define USB2_RX_REG0 0x20
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#define USB2_RX_REG1 0x24
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#define USB2_RX_REG2 0x28
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#define USB2_ANA_REG0 0x30
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#define USB2_ANA_REG1 0x34
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#define USB2_ANA_REG2 0x38
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#define USB2_DIG_REG0 0x3C
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#define USB2_DIG_REG1 0x40
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#define USB2_DIG_REG2 0x44
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#define USB2_DIG_REG3 0x48
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#define USB2_TEST_REG0 0x4C
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#define USB2_TEST_REG1 0x50
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#define USB2_TEST_REG2 0x54
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#define USB2_CHARGER_REG0 0x58
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#define USB2_OTG_REG0 0x5C
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#define USB2_PHY_MON0 0x60
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#define USB2_RESETVE_REG0 0x64
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#define USB2_ICID_REG0 0x78
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#define USB2_ICID_REG1 0x7C
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/* USB2_PLL_REG0 */
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/* This is for Ax stepping */
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#define USB2_PLL_FBDIV_SHIFT_MMP3 0
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#define USB2_PLL_FBDIV_MASK_MMP3 (0xFF << 0)
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#define USB2_PLL_REFDIV_SHIFT_MMP3 8
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#define USB2_PLL_REFDIV_MASK_MMP3 (0xF << 8)
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#define USB2_PLL_VDD12_SHIFT_MMP3 12
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#define USB2_PLL_VDD18_SHIFT_MMP3 14
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/* This is for B0 stepping */
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#define USB2_PLL_FBDIV_SHIFT_MMP3_B0 0
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#define USB2_PLL_REFDIV_SHIFT_MMP3_B0 9
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#define USB2_PLL_VDD18_SHIFT_MMP3_B0 14
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#define USB2_PLL_FBDIV_MASK_MMP3_B0 0x01FF
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#define USB2_PLL_REFDIV_MASK_MMP3_B0 0x3E00
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#define USB2_PLL_CAL12_SHIFT_MMP3 0
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#define USB2_PLL_CALI12_MASK_MMP3 (0x3 << 0)
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#define USB2_PLL_VCOCAL_START_SHIFT_MMP3 2
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#define USB2_PLL_KVCO_SHIFT_MMP3 4
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#define USB2_PLL_KVCO_MASK_MMP3 (0x7<<4)
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#define USB2_PLL_ICP_SHIFT_MMP3 8
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#define USB2_PLL_ICP_MASK_MMP3 (0x7<<8)
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#define USB2_PLL_LOCK_BYPASS_SHIFT_MMP3 12
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#define USB2_PLL_PU_PLL_SHIFT_MMP3 13
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#define USB2_PLL_PU_PLL_MASK (0x1 << 13)
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#define USB2_PLL_READY_MASK_MMP3 (0x1 << 15)
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/* USB2_TX_REG0 */
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#define USB2_TX_IMPCAL_VTH_SHIFT_MMP3 8
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#define USB2_TX_IMPCAL_VTH_MASK_MMP3 (0x7 << 8)
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#define USB2_TX_RCAL_START_SHIFT_MMP3 13
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/* USB2_TX_REG1 */
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#define USB2_TX_CK60_PHSEL_SHIFT_MMP3 0
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#define USB2_TX_CK60_PHSEL_MASK_MMP3 (0xf << 0)
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#define USB2_TX_AMP_SHIFT_MMP3 4
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#define USB2_TX_AMP_MASK_MMP3 (0x7 << 4)
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#define USB2_TX_VDD12_SHIFT_MMP3 8
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#define USB2_TX_VDD12_MASK_MMP3 (0x3 << 8)
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/* USB2_TX_REG2 */
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#define USB2_TX_DRV_SLEWRATE_SHIFT 10
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/* USB2_RX_REG0 */
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#define USB2_RX_SQ_THRESH_SHIFT_MMP3 4
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#define USB2_RX_SQ_THRESH_MASK_MMP3 (0xf << 4)
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#define USB2_RX_SQ_LENGTH_SHIFT_MMP3 10
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#define USB2_RX_SQ_LENGTH_MASK_MMP3 (0x3 << 10)
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/* USB2_ANA_REG1*/
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#define USB2_ANA_PU_ANA_SHIFT_MMP3 14
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/* USB2_OTG_REG0 */
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#define USB2_OTG_PU_OTG_SHIFT_MMP3 3
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/* fsic registers */
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#define FSIC_MISC 0x4
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#define FSIC_INT 0x28
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#define FSIC_CTRL 0x30
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/* HSIC registers */
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#define HSIC_PAD_CTRL 0x4
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#define HSIC_CTRL 0x8
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#define HSIC_CTRL_HSIC_ENABLE (1<<7)
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#define HSIC_CTRL_PLL_BYPASS (1<<4)
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#define TEST_GRP_0 0xc
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#define TEST_GRP_1 0x10
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#define HSIC_INT 0x14
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#define HSIC_INT_READY_INT_EN (1<<10)
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#define HSIC_INT_CONNECT_INT_EN (1<<9)
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#define HSIC_INT_CORE_INT_EN (1<<8)
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#define HSIC_INT_HS_READY (1<<2)
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#define HSIC_INT_CONNECT (1<<1)
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#define HSIC_INT_CORE (1<<0)
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#define HSIC_CONFIG 0x18
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#define USBHSIC_CTRL 0x20
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#define HSIC_USB_CTRL 0x28
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#define HSIC_USB_CTRL_CLKEN 1
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#define HSIC_USB_CLK_PHY 0x0
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#define HSIC_USB_CLK_PMU 0x1
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#endif /* __ASM_ARCH_PXA_U2O_H */
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