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![John Oldman](/assets/img/avatar_default.png)
Fixed a warning message spelling issue. Signed-off-by: John Oldman <john.oldman@polehill.co.uk> Signed-off-by: Jens Axboe <axboe@kernel.dk>
906 lines
24 KiB
C
906 lines
24 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* sata_inic162x.c - Driver for Initio 162x SATA controllers
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*
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* Copyright 2006 SUSE Linux Products GmbH
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* Copyright 2006 Tejun Heo <teheo@novell.com>
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*
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* **** WARNING ****
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*
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* This driver never worked properly and unfortunately data corruption is
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* relatively common. There isn't anyone working on the driver and there's
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* no support from the vendor. Do not use this driver in any production
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* environment.
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*
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* http://thread.gmane.org/gmane.linux.debian.devel.bugs.rc/378525/focus=54491
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* https://bugzilla.kernel.org/show_bug.cgi?id=60565
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*
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* *****************
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*
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* This controller is eccentric and easily locks up if something isn't
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* right. Documentation is available at initio's website but it only
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* documents registers (not programming model).
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*
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* This driver has interesting history. The first version was written
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* from the documentation and a 2.4 IDE driver posted on a Taiwan
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* company, which didn't use any IDMA features and couldn't handle
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* LBA48. The resulting driver couldn't handle LBA48 devices either
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* making it pretty useless.
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*
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* After a while, initio picked the driver up, renamed it to
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* sata_initio162x, updated it to use IDMA for ATA DMA commands and
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* posted it on their website. It only used ATA_PROT_DMA for IDMA and
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* attaching both devices and issuing IDMA and !IDMA commands
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* simultaneously broke it due to PIRQ masking interaction but it did
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* show how to use the IDMA (ADMA + some initio specific twists)
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* engine.
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*
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* Then, I picked up their changes again and here's the usable driver
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* which uses IDMA for everything. Everything works now including
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* LBA48, CD/DVD burning, suspend/resume and hotplug. There are some
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* issues tho. Result Tf is not resported properly, NCQ isn't
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* supported yet and CD/DVD writing works with DMA assisted PIO
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* protocol (which, for native SATA devices, shouldn't cause any
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* noticeable difference).
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*
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* Anyways, so, here's finally a working driver for inic162x. Enjoy!
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*
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* initio: If you guys wanna improve the driver regarding result TF
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* access and other stuff, please feel free to contact me. I'll be
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* happy to assist.
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*/
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#include <linux/gfp.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#include <linux/blkdev.h>
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#include <scsi/scsi_device.h>
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#define DRV_NAME "sata_inic162x"
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#define DRV_VERSION "0.4"
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enum {
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MMIO_BAR_PCI = 5,
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MMIO_BAR_CARDBUS = 1,
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NR_PORTS = 2,
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IDMA_CPB_TBL_SIZE = 4 * 32,
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INIC_DMA_BOUNDARY = 0xffffff,
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HOST_ACTRL = 0x08,
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HOST_CTL = 0x7c,
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HOST_STAT = 0x7e,
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HOST_IRQ_STAT = 0xbc,
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HOST_IRQ_MASK = 0xbe,
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PORT_SIZE = 0x40,
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/* registers for ATA TF operation */
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PORT_TF_DATA = 0x00,
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PORT_TF_FEATURE = 0x01,
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PORT_TF_NSECT = 0x02,
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PORT_TF_LBAL = 0x03,
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PORT_TF_LBAM = 0x04,
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PORT_TF_LBAH = 0x05,
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PORT_TF_DEVICE = 0x06,
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PORT_TF_COMMAND = 0x07,
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PORT_TF_ALT_STAT = 0x08,
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PORT_IRQ_STAT = 0x09,
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PORT_IRQ_MASK = 0x0a,
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PORT_PRD_CTL = 0x0b,
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PORT_PRD_ADDR = 0x0c,
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PORT_PRD_XFERLEN = 0x10,
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PORT_CPB_CPBLAR = 0x18,
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PORT_CPB_PTQFIFO = 0x1c,
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/* IDMA register */
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PORT_IDMA_CTL = 0x14,
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PORT_IDMA_STAT = 0x16,
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PORT_RPQ_FIFO = 0x1e,
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PORT_RPQ_CNT = 0x1f,
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PORT_SCR = 0x20,
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/* HOST_CTL bits */
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HCTL_LEDEN = (1 << 3), /* enable LED operation */
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HCTL_IRQOFF = (1 << 8), /* global IRQ off */
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HCTL_FTHD0 = (1 << 10), /* fifo threshold 0 */
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HCTL_FTHD1 = (1 << 11), /* fifo threshold 1*/
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HCTL_PWRDWN = (1 << 12), /* power down PHYs */
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HCTL_SOFTRST = (1 << 13), /* global reset (no phy reset) */
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HCTL_RPGSEL = (1 << 15), /* register page select */
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HCTL_KNOWN_BITS = HCTL_IRQOFF | HCTL_PWRDWN | HCTL_SOFTRST |
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HCTL_RPGSEL,
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/* HOST_IRQ_(STAT|MASK) bits */
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HIRQ_PORT0 = (1 << 0),
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HIRQ_PORT1 = (1 << 1),
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HIRQ_SOFT = (1 << 14),
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HIRQ_GLOBAL = (1 << 15), /* STAT only */
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/* PORT_IRQ_(STAT|MASK) bits */
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PIRQ_OFFLINE = (1 << 0), /* device unplugged */
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PIRQ_ONLINE = (1 << 1), /* device plugged */
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PIRQ_COMPLETE = (1 << 2), /* completion interrupt */
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PIRQ_FATAL = (1 << 3), /* fatal error */
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PIRQ_ATA = (1 << 4), /* ATA interrupt */
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PIRQ_REPLY = (1 << 5), /* reply FIFO not empty */
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PIRQ_PENDING = (1 << 7), /* port IRQ pending (STAT only) */
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PIRQ_ERR = PIRQ_OFFLINE | PIRQ_ONLINE | PIRQ_FATAL,
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PIRQ_MASK_DEFAULT = PIRQ_REPLY | PIRQ_ATA,
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PIRQ_MASK_FREEZE = 0xff,
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/* PORT_PRD_CTL bits */
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PRD_CTL_START = (1 << 0),
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PRD_CTL_WR = (1 << 3),
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PRD_CTL_DMAEN = (1 << 7), /* DMA enable */
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/* PORT_IDMA_CTL bits */
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IDMA_CTL_RST_ATA = (1 << 2), /* hardreset ATA bus */
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IDMA_CTL_RST_IDMA = (1 << 5), /* reset IDMA machinery */
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IDMA_CTL_GO = (1 << 7), /* IDMA mode go */
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IDMA_CTL_ATA_NIEN = (1 << 8), /* ATA IRQ disable */
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/* PORT_IDMA_STAT bits */
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IDMA_STAT_PERR = (1 << 0), /* PCI ERROR MODE */
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IDMA_STAT_CPBERR = (1 << 1), /* ADMA CPB error */
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IDMA_STAT_LGCY = (1 << 3), /* ADMA legacy */
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IDMA_STAT_UIRQ = (1 << 4), /* ADMA unsolicited irq */
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IDMA_STAT_STPD = (1 << 5), /* ADMA stopped */
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IDMA_STAT_PSD = (1 << 6), /* ADMA pause */
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IDMA_STAT_DONE = (1 << 7), /* ADMA done */
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IDMA_STAT_ERR = IDMA_STAT_PERR | IDMA_STAT_CPBERR,
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/* CPB Control Flags*/
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CPB_CTL_VALID = (1 << 0), /* CPB valid */
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CPB_CTL_QUEUED = (1 << 1), /* queued command */
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CPB_CTL_DATA = (1 << 2), /* data, rsvd in datasheet */
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CPB_CTL_IEN = (1 << 3), /* PCI interrupt enable */
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CPB_CTL_DEVDIR = (1 << 4), /* device direction control */
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/* CPB Response Flags */
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CPB_RESP_DONE = (1 << 0), /* ATA command complete */
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CPB_RESP_REL = (1 << 1), /* ATA release */
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CPB_RESP_IGNORED = (1 << 2), /* CPB ignored */
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CPB_RESP_ATA_ERR = (1 << 3), /* ATA command error */
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CPB_RESP_SPURIOUS = (1 << 4), /* ATA spurious interrupt error */
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CPB_RESP_UNDERFLOW = (1 << 5), /* APRD deficiency length error */
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CPB_RESP_OVERFLOW = (1 << 6), /* APRD exccess length error */
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CPB_RESP_CPB_ERR = (1 << 7), /* CPB error flag */
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/* PRD Control Flags */
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PRD_DRAIN = (1 << 1), /* ignore data excess */
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PRD_CDB = (1 << 2), /* atapi packet command pointer */
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PRD_DIRECT_INTR = (1 << 3), /* direct interrupt */
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PRD_DMA = (1 << 4), /* data transfer method */
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PRD_WRITE = (1 << 5), /* data dir, rsvd in datasheet */
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PRD_IOM = (1 << 6), /* io/memory transfer */
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PRD_END = (1 << 7), /* APRD chain end */
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};
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/* Comman Parameter Block */
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struct inic_cpb {
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u8 resp_flags; /* Response Flags */
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u8 error; /* ATA Error */
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u8 status; /* ATA Status */
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u8 ctl_flags; /* Control Flags */
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__le32 len; /* Total Transfer Length */
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__le32 prd; /* First PRD pointer */
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u8 rsvd[4];
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/* 16 bytes */
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u8 feature; /* ATA Feature */
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u8 hob_feature; /* ATA Ex. Feature */
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u8 device; /* ATA Device/Head */
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u8 mirctl; /* Mirror Control */
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u8 nsect; /* ATA Sector Count */
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u8 hob_nsect; /* ATA Ex. Sector Count */
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u8 lbal; /* ATA Sector Number */
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u8 hob_lbal; /* ATA Ex. Sector Number */
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u8 lbam; /* ATA Cylinder Low */
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u8 hob_lbam; /* ATA Ex. Cylinder Low */
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u8 lbah; /* ATA Cylinder High */
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u8 hob_lbah; /* ATA Ex. Cylinder High */
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u8 command; /* ATA Command */
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u8 ctl; /* ATA Control */
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u8 slave_error; /* Slave ATA Error */
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u8 slave_status; /* Slave ATA Status */
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/* 32 bytes */
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} __packed;
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/* Physical Region Descriptor */
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struct inic_prd {
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__le32 mad; /* Physical Memory Address */
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__le16 len; /* Transfer Length */
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u8 rsvd;
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u8 flags; /* Control Flags */
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} __packed;
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struct inic_pkt {
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struct inic_cpb cpb;
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struct inic_prd prd[LIBATA_MAX_PRD + 1]; /* + 1 for cdb */
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u8 cdb[ATAPI_CDB_LEN];
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} __packed;
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struct inic_host_priv {
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void __iomem *mmio_base;
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u16 cached_hctl;
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};
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struct inic_port_priv {
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struct inic_pkt *pkt;
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dma_addr_t pkt_dma;
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u32 *cpb_tbl;
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dma_addr_t cpb_tbl_dma;
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};
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static struct scsi_host_template inic_sht = {
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ATA_BASE_SHT(DRV_NAME),
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.sg_tablesize = LIBATA_MAX_PRD, /* maybe it can be larger? */
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/*
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* This controller is braindamaged. dma_boundary is 0xffff like others
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* but it will lock up the whole machine HARD if 65536 byte PRD entry
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* is fed. Reduce maximum segment size.
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*/
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.dma_boundary = INIC_DMA_BOUNDARY,
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.max_segment_size = 65536 - 512,
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};
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static const int scr_map[] = {
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[SCR_STATUS] = 0,
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[SCR_ERROR] = 1,
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[SCR_CONTROL] = 2,
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};
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static void __iomem *inic_port_base(struct ata_port *ap)
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{
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struct inic_host_priv *hpriv = ap->host->private_data;
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return hpriv->mmio_base + ap->port_no * PORT_SIZE;
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}
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static void inic_reset_port(void __iomem *port_base)
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{
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void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
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/* stop IDMA engine */
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readw(idma_ctl); /* flush */
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msleep(1);
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/* mask IRQ and assert reset */
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writew(IDMA_CTL_RST_IDMA, idma_ctl);
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readw(idma_ctl); /* flush */
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msleep(1);
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/* release reset */
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writew(0, idma_ctl);
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/* clear irq */
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writeb(0xff, port_base + PORT_IRQ_STAT);
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}
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static int inic_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val)
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{
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void __iomem *scr_addr = inic_port_base(link->ap) + PORT_SCR;
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if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
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return -EINVAL;
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*val = readl(scr_addr + scr_map[sc_reg] * 4);
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/* this controller has stuck DIAG.N, ignore it */
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if (sc_reg == SCR_ERROR)
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*val &= ~SERR_PHYRDY_CHG;
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return 0;
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}
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static int inic_scr_write(struct ata_link *link, unsigned sc_reg, u32 val)
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{
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void __iomem *scr_addr = inic_port_base(link->ap) + PORT_SCR;
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if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
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return -EINVAL;
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writel(val, scr_addr + scr_map[sc_reg] * 4);
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return 0;
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}
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static void inic_stop_idma(struct ata_port *ap)
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{
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void __iomem *port_base = inic_port_base(ap);
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readb(port_base + PORT_RPQ_FIFO);
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readb(port_base + PORT_RPQ_CNT);
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writew(0, port_base + PORT_IDMA_CTL);
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}
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static void inic_host_err_intr(struct ata_port *ap, u8 irq_stat, u16 idma_stat)
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{
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struct ata_eh_info *ehi = &ap->link.eh_info;
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struct inic_port_priv *pp = ap->private_data;
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struct inic_cpb *cpb = &pp->pkt->cpb;
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bool freeze = false;
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ata_ehi_clear_desc(ehi);
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ata_ehi_push_desc(ehi, "irq_stat=0x%x idma_stat=0x%x",
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irq_stat, idma_stat);
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inic_stop_idma(ap);
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if (irq_stat & (PIRQ_OFFLINE | PIRQ_ONLINE)) {
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ata_ehi_push_desc(ehi, "hotplug");
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ata_ehi_hotplugged(ehi);
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freeze = true;
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}
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if (idma_stat & IDMA_STAT_PERR) {
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ata_ehi_push_desc(ehi, "PCI error");
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freeze = true;
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}
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if (idma_stat & IDMA_STAT_CPBERR) {
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ata_ehi_push_desc(ehi, "CPB error");
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if (cpb->resp_flags & CPB_RESP_IGNORED) {
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__ata_ehi_push_desc(ehi, " ignored");
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ehi->err_mask |= AC_ERR_INVALID;
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freeze = true;
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}
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if (cpb->resp_flags & CPB_RESP_ATA_ERR)
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ehi->err_mask |= AC_ERR_DEV;
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if (cpb->resp_flags & CPB_RESP_SPURIOUS) {
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__ata_ehi_push_desc(ehi, " spurious-intr");
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ehi->err_mask |= AC_ERR_HSM;
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freeze = true;
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}
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if (cpb->resp_flags &
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(CPB_RESP_UNDERFLOW | CPB_RESP_OVERFLOW)) {
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__ata_ehi_push_desc(ehi, " data-over/underflow");
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ehi->err_mask |= AC_ERR_HSM;
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freeze = true;
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}
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}
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if (freeze)
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ata_port_freeze(ap);
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else
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ata_port_abort(ap);
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}
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static void inic_host_intr(struct ata_port *ap)
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{
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void __iomem *port_base = inic_port_base(ap);
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struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
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u8 irq_stat;
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u16 idma_stat;
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/* read and clear IRQ status */
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irq_stat = readb(port_base + PORT_IRQ_STAT);
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writeb(irq_stat, port_base + PORT_IRQ_STAT);
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idma_stat = readw(port_base + PORT_IDMA_STAT);
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if (unlikely((irq_stat & PIRQ_ERR) || (idma_stat & IDMA_STAT_ERR)))
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inic_host_err_intr(ap, irq_stat, idma_stat);
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if (unlikely(!qc))
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goto spurious;
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if (likely(idma_stat & IDMA_STAT_DONE)) {
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inic_stop_idma(ap);
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/* Depending on circumstances, device error
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* isn't reported by IDMA, check it explicitly.
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*/
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if (unlikely(readb(port_base + PORT_TF_COMMAND) &
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(ATA_DF | ATA_ERR)))
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qc->err_mask |= AC_ERR_DEV;
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ata_qc_complete(qc);
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return;
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}
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spurious:
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ata_port_warn(ap, "unhandled interrupt: cmd=0x%x irq_stat=0x%x idma_stat=0x%x\n",
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qc ? qc->tf.command : 0xff, irq_stat, idma_stat);
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}
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static irqreturn_t inic_interrupt(int irq, void *dev_instance)
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{
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struct ata_host *host = dev_instance;
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struct inic_host_priv *hpriv = host->private_data;
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u16 host_irq_stat;
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int i, handled = 0;
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host_irq_stat = readw(hpriv->mmio_base + HOST_IRQ_STAT);
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if (unlikely(!(host_irq_stat & HIRQ_GLOBAL)))
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goto out;
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spin_lock(&host->lock);
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for (i = 0; i < NR_PORTS; i++)
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if (host_irq_stat & (HIRQ_PORT0 << i)) {
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inic_host_intr(host->ports[i]);
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handled++;
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}
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spin_unlock(&host->lock);
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out:
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return IRQ_RETVAL(handled);
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}
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static int inic_check_atapi_dma(struct ata_queued_cmd *qc)
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{
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/* For some reason ATAPI_PROT_DMA doesn't work for some
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* commands including writes and other misc ops. Use PIO
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* protocol instead, which BTW is driven by the DMA engine
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* anyway, so it shouldn't make much difference for native
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* SATA devices.
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*/
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if (atapi_cmd_type(qc->cdb[0]) == READ)
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return 0;
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return 1;
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}
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static void inic_fill_sg(struct inic_prd *prd, struct ata_queued_cmd *qc)
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|
{
|
|
struct scatterlist *sg;
|
|
unsigned int si;
|
|
u8 flags = 0;
|
|
|
|
if (qc->tf.flags & ATA_TFLAG_WRITE)
|
|
flags |= PRD_WRITE;
|
|
|
|
if (ata_is_dma(qc->tf.protocol))
|
|
flags |= PRD_DMA;
|
|
|
|
for_each_sg(qc->sg, sg, qc->n_elem, si) {
|
|
prd->mad = cpu_to_le32(sg_dma_address(sg));
|
|
prd->len = cpu_to_le16(sg_dma_len(sg));
|
|
prd->flags = flags;
|
|
prd++;
|
|
}
|
|
|
|
WARN_ON(!si);
|
|
prd[-1].flags |= PRD_END;
|
|
}
|
|
|
|
static enum ata_completion_errors inic_qc_prep(struct ata_queued_cmd *qc)
|
|
{
|
|
struct inic_port_priv *pp = qc->ap->private_data;
|
|
struct inic_pkt *pkt = pp->pkt;
|
|
struct inic_cpb *cpb = &pkt->cpb;
|
|
struct inic_prd *prd = pkt->prd;
|
|
bool is_atapi = ata_is_atapi(qc->tf.protocol);
|
|
bool is_data = ata_is_data(qc->tf.protocol);
|
|
unsigned int cdb_len = 0;
|
|
|
|
VPRINTK("ENTER\n");
|
|
|
|
if (is_atapi)
|
|
cdb_len = qc->dev->cdb_len;
|
|
|
|
/* prepare packet, based on initio driver */
|
|
memset(pkt, 0, sizeof(struct inic_pkt));
|
|
|
|
cpb->ctl_flags = CPB_CTL_VALID | CPB_CTL_IEN;
|
|
if (is_atapi || is_data)
|
|
cpb->ctl_flags |= CPB_CTL_DATA;
|
|
|
|
cpb->len = cpu_to_le32(qc->nbytes + cdb_len);
|
|
cpb->prd = cpu_to_le32(pp->pkt_dma + offsetof(struct inic_pkt, prd));
|
|
|
|
cpb->device = qc->tf.device;
|
|
cpb->feature = qc->tf.feature;
|
|
cpb->nsect = qc->tf.nsect;
|
|
cpb->lbal = qc->tf.lbal;
|
|
cpb->lbam = qc->tf.lbam;
|
|
cpb->lbah = qc->tf.lbah;
|
|
|
|
if (qc->tf.flags & ATA_TFLAG_LBA48) {
|
|
cpb->hob_feature = qc->tf.hob_feature;
|
|
cpb->hob_nsect = qc->tf.hob_nsect;
|
|
cpb->hob_lbal = qc->tf.hob_lbal;
|
|
cpb->hob_lbam = qc->tf.hob_lbam;
|
|
cpb->hob_lbah = qc->tf.hob_lbah;
|
|
}
|
|
|
|
cpb->command = qc->tf.command;
|
|
/* don't load ctl - dunno why. it's like that in the initio driver */
|
|
|
|
/* setup PRD for CDB */
|
|
if (is_atapi) {
|
|
memcpy(pkt->cdb, qc->cdb, ATAPI_CDB_LEN);
|
|
prd->mad = cpu_to_le32(pp->pkt_dma +
|
|
offsetof(struct inic_pkt, cdb));
|
|
prd->len = cpu_to_le16(cdb_len);
|
|
prd->flags = PRD_CDB | PRD_WRITE;
|
|
if (!is_data)
|
|
prd->flags |= PRD_END;
|
|
prd++;
|
|
}
|
|
|
|
/* setup sg table */
|
|
if (is_data)
|
|
inic_fill_sg(prd, qc);
|
|
|
|
pp->cpb_tbl[0] = pp->pkt_dma;
|
|
|
|
return AC_ERR_OK;
|
|
}
|
|
|
|
static unsigned int inic_qc_issue(struct ata_queued_cmd *qc)
|
|
{
|
|
struct ata_port *ap = qc->ap;
|
|
void __iomem *port_base = inic_port_base(ap);
|
|
|
|
/* fire up the ADMA engine */
|
|
writew(HCTL_FTHD0 | HCTL_LEDEN, port_base + HOST_CTL);
|
|
writew(IDMA_CTL_GO, port_base + PORT_IDMA_CTL);
|
|
writeb(0, port_base + PORT_CPB_PTQFIFO);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void inic_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
|
|
{
|
|
void __iomem *port_base = inic_port_base(ap);
|
|
|
|
tf->feature = readb(port_base + PORT_TF_FEATURE);
|
|
tf->nsect = readb(port_base + PORT_TF_NSECT);
|
|
tf->lbal = readb(port_base + PORT_TF_LBAL);
|
|
tf->lbam = readb(port_base + PORT_TF_LBAM);
|
|
tf->lbah = readb(port_base + PORT_TF_LBAH);
|
|
tf->device = readb(port_base + PORT_TF_DEVICE);
|
|
tf->command = readb(port_base + PORT_TF_COMMAND);
|
|
}
|
|
|
|
static bool inic_qc_fill_rtf(struct ata_queued_cmd *qc)
|
|
{
|
|
struct ata_taskfile *rtf = &qc->result_tf;
|
|
struct ata_taskfile tf;
|
|
|
|
/* FIXME: Except for status and error, result TF access
|
|
* doesn't work. I tried reading from BAR0/2, CPB and BAR5.
|
|
* None works regardless of which command interface is used.
|
|
* For now return true iff status indicates device error.
|
|
* This means that we're reporting bogus sector for RW
|
|
* failures. Eeekk....
|
|
*/
|
|
inic_tf_read(qc->ap, &tf);
|
|
|
|
if (!(tf.command & ATA_ERR))
|
|
return false;
|
|
|
|
rtf->command = tf.command;
|
|
rtf->feature = tf.feature;
|
|
return true;
|
|
}
|
|
|
|
static void inic_freeze(struct ata_port *ap)
|
|
{
|
|
void __iomem *port_base = inic_port_base(ap);
|
|
|
|
writeb(PIRQ_MASK_FREEZE, port_base + PORT_IRQ_MASK);
|
|
writeb(0xff, port_base + PORT_IRQ_STAT);
|
|
}
|
|
|
|
static void inic_thaw(struct ata_port *ap)
|
|
{
|
|
void __iomem *port_base = inic_port_base(ap);
|
|
|
|
writeb(0xff, port_base + PORT_IRQ_STAT);
|
|
writeb(PIRQ_MASK_DEFAULT, port_base + PORT_IRQ_MASK);
|
|
}
|
|
|
|
static int inic_check_ready(struct ata_link *link)
|
|
{
|
|
void __iomem *port_base = inic_port_base(link->ap);
|
|
|
|
return ata_check_ready(readb(port_base + PORT_TF_COMMAND));
|
|
}
|
|
|
|
/*
|
|
* SRST and SControl hardreset don't give valid signature on this
|
|
* controller. Only controller specific hardreset mechanism works.
|
|
*/
|
|
static int inic_hardreset(struct ata_link *link, unsigned int *class,
|
|
unsigned long deadline)
|
|
{
|
|
struct ata_port *ap = link->ap;
|
|
void __iomem *port_base = inic_port_base(ap);
|
|
void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
|
|
const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
|
|
int rc;
|
|
|
|
/* hammer it into sane state */
|
|
inic_reset_port(port_base);
|
|
|
|
writew(IDMA_CTL_RST_ATA, idma_ctl);
|
|
readw(idma_ctl); /* flush */
|
|
ata_msleep(ap, 1);
|
|
writew(0, idma_ctl);
|
|
|
|
rc = sata_link_resume(link, timing, deadline);
|
|
if (rc) {
|
|
ata_link_warn(link,
|
|
"failed to resume link after reset (errno=%d)\n",
|
|
rc);
|
|
return rc;
|
|
}
|
|
|
|
*class = ATA_DEV_NONE;
|
|
if (ata_link_online(link)) {
|
|
struct ata_taskfile tf;
|
|
|
|
/* wait for link to become ready */
|
|
rc = ata_wait_after_reset(link, deadline, inic_check_ready);
|
|
/* link occupied, -ENODEV too is an error */
|
|
if (rc) {
|
|
ata_link_warn(link,
|
|
"device not ready after hardreset (errno=%d)\n",
|
|
rc);
|
|
return rc;
|
|
}
|
|
|
|
inic_tf_read(ap, &tf);
|
|
*class = ata_dev_classify(&tf);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void inic_error_handler(struct ata_port *ap)
|
|
{
|
|
void __iomem *port_base = inic_port_base(ap);
|
|
|
|
inic_reset_port(port_base);
|
|
ata_std_error_handler(ap);
|
|
}
|
|
|
|
static void inic_post_internal_cmd(struct ata_queued_cmd *qc)
|
|
{
|
|
/* make DMA engine forget about the failed command */
|
|
if (qc->flags & ATA_QCFLAG_FAILED)
|
|
inic_reset_port(inic_port_base(qc->ap));
|
|
}
|
|
|
|
static void init_port(struct ata_port *ap)
|
|
{
|
|
void __iomem *port_base = inic_port_base(ap);
|
|
struct inic_port_priv *pp = ap->private_data;
|
|
|
|
/* clear packet and CPB table */
|
|
memset(pp->pkt, 0, sizeof(struct inic_pkt));
|
|
memset(pp->cpb_tbl, 0, IDMA_CPB_TBL_SIZE);
|
|
|
|
/* setup CPB lookup table addresses */
|
|
writel(pp->cpb_tbl_dma, port_base + PORT_CPB_CPBLAR);
|
|
}
|
|
|
|
static int inic_port_resume(struct ata_port *ap)
|
|
{
|
|
init_port(ap);
|
|
return 0;
|
|
}
|
|
|
|
static int inic_port_start(struct ata_port *ap)
|
|
{
|
|
struct device *dev = ap->host->dev;
|
|
struct inic_port_priv *pp;
|
|
|
|
/* alloc and initialize private data */
|
|
pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
|
|
if (!pp)
|
|
return -ENOMEM;
|
|
ap->private_data = pp;
|
|
|
|
/* Alloc resources */
|
|
pp->pkt = dmam_alloc_coherent(dev, sizeof(struct inic_pkt),
|
|
&pp->pkt_dma, GFP_KERNEL);
|
|
if (!pp->pkt)
|
|
return -ENOMEM;
|
|
|
|
pp->cpb_tbl = dmam_alloc_coherent(dev, IDMA_CPB_TBL_SIZE,
|
|
&pp->cpb_tbl_dma, GFP_KERNEL);
|
|
if (!pp->cpb_tbl)
|
|
return -ENOMEM;
|
|
|
|
init_port(ap);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct ata_port_operations inic_port_ops = {
|
|
.inherits = &sata_port_ops,
|
|
|
|
.check_atapi_dma = inic_check_atapi_dma,
|
|
.qc_prep = inic_qc_prep,
|
|
.qc_issue = inic_qc_issue,
|
|
.qc_fill_rtf = inic_qc_fill_rtf,
|
|
|
|
.freeze = inic_freeze,
|
|
.thaw = inic_thaw,
|
|
.hardreset = inic_hardreset,
|
|
.error_handler = inic_error_handler,
|
|
.post_internal_cmd = inic_post_internal_cmd,
|
|
|
|
.scr_read = inic_scr_read,
|
|
.scr_write = inic_scr_write,
|
|
|
|
.port_resume = inic_port_resume,
|
|
.port_start = inic_port_start,
|
|
};
|
|
|
|
static const struct ata_port_info inic_port_info = {
|
|
.flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
|
|
.pio_mask = ATA_PIO4,
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
.udma_mask = ATA_UDMA6,
|
|
.port_ops = &inic_port_ops
|
|
};
|
|
|
|
static int init_controller(void __iomem *mmio_base, u16 hctl)
|
|
{
|
|
int i;
|
|
u16 val;
|
|
|
|
hctl &= ~HCTL_KNOWN_BITS;
|
|
|
|
/* Soft reset whole controller. Spec says reset duration is 3
|
|
* PCI clocks, be generous and give it 10ms.
|
|
*/
|
|
writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL);
|
|
readw(mmio_base + HOST_CTL); /* flush */
|
|
|
|
for (i = 0; i < 10; i++) {
|
|
msleep(1);
|
|
val = readw(mmio_base + HOST_CTL);
|
|
if (!(val & HCTL_SOFTRST))
|
|
break;
|
|
}
|
|
|
|
if (val & HCTL_SOFTRST)
|
|
return -EIO;
|
|
|
|
/* mask all interrupts and reset ports */
|
|
for (i = 0; i < NR_PORTS; i++) {
|
|
void __iomem *port_base = mmio_base + i * PORT_SIZE;
|
|
|
|
writeb(0xff, port_base + PORT_IRQ_MASK);
|
|
inic_reset_port(port_base);
|
|
}
|
|
|
|
/* port IRQ is masked now, unmask global IRQ */
|
|
writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL);
|
|
val = readw(mmio_base + HOST_IRQ_MASK);
|
|
val &= ~(HIRQ_PORT0 | HIRQ_PORT1);
|
|
writew(val, mmio_base + HOST_IRQ_MASK);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int inic_pci_device_resume(struct pci_dev *pdev)
|
|
{
|
|
struct ata_host *host = pci_get_drvdata(pdev);
|
|
struct inic_host_priv *hpriv = host->private_data;
|
|
int rc;
|
|
|
|
rc = ata_pci_device_do_resume(pdev);
|
|
if (rc)
|
|
return rc;
|
|
|
|
if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
|
|
rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl);
|
|
if (rc)
|
|
return rc;
|
|
}
|
|
|
|
ata_host_resume(host);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
{
|
|
const struct ata_port_info *ppi[] = { &inic_port_info, NULL };
|
|
struct ata_host *host;
|
|
struct inic_host_priv *hpriv;
|
|
void __iomem * const *iomap;
|
|
int mmio_bar;
|
|
int i, rc;
|
|
|
|
ata_print_version_once(&pdev->dev, DRV_VERSION);
|
|
|
|
dev_alert(&pdev->dev, "inic162x support is broken with common data corruption issues and will be disabled by default, contact linux-ide@vger.kernel.org if in production use\n");
|
|
|
|
/* alloc host */
|
|
host = ata_host_alloc_pinfo(&pdev->dev, ppi, NR_PORTS);
|
|
hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
|
|
if (!host || !hpriv)
|
|
return -ENOMEM;
|
|
|
|
host->private_data = hpriv;
|
|
|
|
/* Acquire resources and fill host. Note that PCI and cardbus
|
|
* use different BARs.
|
|
*/
|
|
rc = pcim_enable_device(pdev);
|
|
if (rc)
|
|
return rc;
|
|
|
|
if (pci_resource_flags(pdev, MMIO_BAR_PCI) & IORESOURCE_MEM)
|
|
mmio_bar = MMIO_BAR_PCI;
|
|
else
|
|
mmio_bar = MMIO_BAR_CARDBUS;
|
|
|
|
rc = pcim_iomap_regions(pdev, 1 << mmio_bar, DRV_NAME);
|
|
if (rc)
|
|
return rc;
|
|
host->iomap = iomap = pcim_iomap_table(pdev);
|
|
hpriv->mmio_base = iomap[mmio_bar];
|
|
hpriv->cached_hctl = readw(hpriv->mmio_base + HOST_CTL);
|
|
|
|
for (i = 0; i < NR_PORTS; i++) {
|
|
struct ata_port *ap = host->ports[i];
|
|
|
|
ata_port_pbar_desc(ap, mmio_bar, -1, "mmio");
|
|
ata_port_pbar_desc(ap, mmio_bar, i * PORT_SIZE, "port");
|
|
}
|
|
|
|
/* Set dma_mask. This devices doesn't support 64bit addressing. */
|
|
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
|
|
if (rc) {
|
|
dev_err(&pdev->dev, "32-bit DMA enable failed\n");
|
|
return rc;
|
|
}
|
|
|
|
rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl);
|
|
if (rc) {
|
|
dev_err(&pdev->dev, "failed to initialize controller\n");
|
|
return rc;
|
|
}
|
|
|
|
pci_set_master(pdev);
|
|
return ata_host_activate(host, pdev->irq, inic_interrupt, IRQF_SHARED,
|
|
&inic_sht);
|
|
}
|
|
|
|
static const struct pci_device_id inic_pci_tbl[] = {
|
|
{ PCI_VDEVICE(INIT, 0x1622), },
|
|
{ },
|
|
};
|
|
|
|
static struct pci_driver inic_pci_driver = {
|
|
.name = DRV_NAME,
|
|
.id_table = inic_pci_tbl,
|
|
#ifdef CONFIG_PM_SLEEP
|
|
.suspend = ata_pci_device_suspend,
|
|
.resume = inic_pci_device_resume,
|
|
#endif
|
|
.probe = inic_init_one,
|
|
.remove = ata_pci_remove_one,
|
|
};
|
|
|
|
module_pci_driver(inic_pci_driver);
|
|
|
|
MODULE_AUTHOR("Tejun Heo");
|
|
MODULE_DESCRIPTION("low-level driver for Initio 162x SATA");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DEVICE_TABLE(pci, inic_pci_tbl);
|
|
MODULE_VERSION(DRV_VERSION);
|