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b39cb1052a
Create the /sys/bus/cxl hierarchy to enumerate: * Memory Devices (per-endpoint control devices) * Memory Address Space Devices (platform address ranges with interleaving, performance, and persistence attributes) * Memory Regions (active provisioned memory from an address space device that is in use as System RAM or delegated to libnvdimm as Persistent Memory regions). For now, only the per-endpoint control devices are registered on the 'cxl' bus. However, going forward it will provide a mechanism to coordinate cross-device interleave. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> (v2) Link: https://lore.kernel.org/r/20210217040958.1354670-4-ben.widawsky@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
29 lines
620 B
C
29 lines
620 B
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2020 Intel Corporation. All rights reserved. */
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#include <linux/device.h>
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#include <linux/module.h>
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/**
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* DOC: cxl bus
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*
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* The CXL bus provides namespace for control devices and a rendezvous
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* point for cross-device interleave coordination.
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*/
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struct bus_type cxl_bus_type = {
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.name = "cxl",
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};
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EXPORT_SYMBOL_GPL(cxl_bus_type);
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static __init int cxl_bus_init(void)
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{
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return bus_register(&cxl_bus_type);
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}
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static void cxl_bus_exit(void)
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{
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bus_unregister(&cxl_bus_type);
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}
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module_init(cxl_bus_init);
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module_exit(cxl_bus_exit);
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MODULE_LICENSE("GPL v2");
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