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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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b9bb868e2f
1.Add X1830 system type for cat /proc/cpuinfo to give out X1830. 2.Change "PRID_IMP_XBURST" to "PRID_IMP_XBURST_REV1" and add a new "PRID_IMP_XBURST_REV2" for new Ingenic CPUs which has XBurst with MXU2 SIMD ISA. Notice: 1."PRID_IMP_XBURST_REV2" is corresponds to the latest XBurst processor with 128bit MXU2 SIMD instruction set, not the upcoming XBurst2 processor. This version of the processors fixes issues such as BTB and HPTLB. 2.In order to simplify and reuse the code, the "c->cputype" and the "c->writecombine" and the "__cpu_name[cpu]" in the original "PRID_IMP_XBURST" (now is "PRID_IMP_XBURST_REV1") are removed, and the corresponding settings are abtained through fall-through to "PRID_IMP_XBURST_REV2", which will cause the name that was previously mistakenly called "JZRISC" to become to the real name "XBurst". Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Signed-off-by: Paul Burton <paulburton@kernel.org> Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: yamada.masahiro@socionext.com Cc: tglx@linutronix.de Cc: chenhc@lemote.com Cc: tbogendoerfer@suse.de Cc: paul.burton@mips.com Cc: paul@crapouillou.net Cc: jhogan@kernel.org Cc: fancer.lancer@gmail.com Cc: ralf@linux-mips.org Cc: jiaxun.yang@flygoat.com
107 lines
2.3 KiB
C
107 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
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* Copyright (C) 2011, Maarten ter Huurne <maarten@treewalker.org>
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* JZ4740 setup code
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <linux/kernel.h>
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#include <linux/libfdt.h>
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#include <linux/of_fdt.h>
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#include <asm/bootinfo.h>
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#include <asm/prom.h>
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#include "reset.h"
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#define JZ4740_EMC_BASE_ADDR 0x13010000
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#define JZ4740_EMC_SDRAM_CTRL 0x80
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static void __init jz4740_detect_mem(void)
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{
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void __iomem *jz_emc_base;
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u32 ctrl, bus, bank, rows, cols;
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phys_addr_t size;
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jz_emc_base = ioremap(JZ4740_EMC_BASE_ADDR, 0x100);
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ctrl = readl(jz_emc_base + JZ4740_EMC_SDRAM_CTRL);
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bus = 2 - ((ctrl >> 31) & 1);
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bank = 1 + ((ctrl >> 19) & 1);
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cols = 8 + ((ctrl >> 26) & 7);
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rows = 11 + ((ctrl >> 20) & 3);
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printk(KERN_DEBUG
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"SDRAM preconfigured: bus:%u bank:%u rows:%u cols:%u\n",
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bus, bank, rows, cols);
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iounmap(jz_emc_base);
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size = 1 << (bus + bank + cols + rows);
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add_memory_region(0, size, BOOT_MEM_RAM);
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}
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static unsigned long __init get_board_mach_type(const void *fdt)
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{
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if (!fdt_node_check_compatible(fdt, 0, "ingenic,x1830"))
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return MACH_INGENIC_X1830;
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if (!fdt_node_check_compatible(fdt, 0, "ingenic,x1000"))
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return MACH_INGENIC_X1000;
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if (!fdt_node_check_compatible(fdt, 0, "ingenic,jz4780"))
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return MACH_INGENIC_JZ4780;
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if (!fdt_node_check_compatible(fdt, 0, "ingenic,jz4770"))
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return MACH_INGENIC_JZ4770;
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return MACH_INGENIC_JZ4740;
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}
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void __init plat_mem_setup(void)
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{
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int offset;
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void *dtb;
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jz4740_reset_init();
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if (__dtb_start != __dtb_end)
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dtb = __dtb_start;
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else
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dtb = (void *)fw_passed_dtb;
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__dt_setup_arch(dtb);
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offset = fdt_path_offset(dtb, "/memory");
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if (offset < 0)
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jz4740_detect_mem();
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mips_machtype = get_board_mach_type(dtb);
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}
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void __init device_tree_init(void)
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{
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if (!initial_boot_params)
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return;
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unflatten_and_copy_device_tree();
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}
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const char *get_system_type(void)
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{
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switch (mips_machtype) {
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case MACH_INGENIC_X1830:
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return "X1830";
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case MACH_INGENIC_X1000:
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return "X1000";
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case MACH_INGENIC_JZ4780:
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return "JZ4780";
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case MACH_INGENIC_JZ4770:
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return "JZ4770";
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default:
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return "JZ4740";
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}
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}
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void __init arch_init_irq(void)
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{
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irqchip_init();
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}
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