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bac89d754b
It adds the core definitions and low-level debug uart support for imx6q. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
65 lines
1.7 KiB
C
65 lines
1.7 KiB
C
/*
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_MXC_IRQS_H__
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#define __ASM_ARCH_MXC_IRQS_H__
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#include <asm-generic/gpio.h>
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/*
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* SoCs with GIC interrupt controller have 160 IRQs, those with TZIC
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* have 128 IRQs, and those with AVIC have 64.
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*
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* To support single image, the biggest number should be defined on
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* top of the list.
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*/
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#if defined CONFIG_ARM_GIC
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#define MXC_INTERNAL_IRQS 160
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#elif defined CONFIG_MXC_TZIC
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#define MXC_INTERNAL_IRQS 128
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#else
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#define MXC_INTERNAL_IRQS 64
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#endif
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#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
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/*
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* The next 16 interrupts are for board specific purposes. Since
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* the kernel can only run on one machine at a time, we can re-use
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* these. If you need more, increase MXC_BOARD_IRQS, but keep it
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* within sensible limits.
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*/
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#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + ARCH_NR_GPIOS)
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#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
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#define MXC_BOARD_IRQS 80
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#else
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#define MXC_BOARD_IRQS 16
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#endif
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#define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)
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#ifdef CONFIG_MX3_IPU_IRQS
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#define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS
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#else
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#define MX3_IPU_IRQS 0
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#endif
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/* REVISIT: Add IPU irqs on IMX51 */
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#define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS)
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extern int imx_irq_set_priority(unsigned char irq, unsigned char prio);
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/* all normal IRQs can be FIQs */
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#define FIQ_START 0
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/* switch between IRQ and FIQ */
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extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type);
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#endif /* __ASM_ARCH_MXC_IRQS_H__ */
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