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![Daniel Vetter](/assets/img/avatar_default.png)
dma_fence_default_wait is the default now, same for the trivial enable_signaling implementation. v2: Also remove the relase hook, dma_fence_free is the default. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Colin Ian King <colin.king@canonical.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: intel-gfx@lists.freedesktop.org Link: https://patchwork.freedesktop.org/patch/msgid/20180704092909.6599-2-daniel.vetter@ffwll.ch
178 lines
5.1 KiB
C
178 lines
5.1 KiB
C
/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "i915_drv.h"
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#include "intel_frontbuffer.h"
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#include "i915_gem_clflush.h"
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static DEFINE_SPINLOCK(clflush_lock);
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struct clflush {
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struct dma_fence dma; /* Must be first for dma_fence_free() */
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struct i915_sw_fence wait;
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struct work_struct work;
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struct drm_i915_gem_object *obj;
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};
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static const char *i915_clflush_get_driver_name(struct dma_fence *fence)
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{
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return DRIVER_NAME;
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}
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static const char *i915_clflush_get_timeline_name(struct dma_fence *fence)
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{
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return "clflush";
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}
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static void i915_clflush_release(struct dma_fence *fence)
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{
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struct clflush *clflush = container_of(fence, typeof(*clflush), dma);
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i915_sw_fence_fini(&clflush->wait);
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BUILD_BUG_ON(offsetof(typeof(*clflush), dma));
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dma_fence_free(&clflush->dma);
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}
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static const struct dma_fence_ops i915_clflush_ops = {
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.get_driver_name = i915_clflush_get_driver_name,
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.get_timeline_name = i915_clflush_get_timeline_name,
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.release = i915_clflush_release,
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};
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static void __i915_do_clflush(struct drm_i915_gem_object *obj)
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{
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GEM_BUG_ON(!i915_gem_object_has_pages(obj));
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drm_clflush_sg(obj->mm.pages);
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intel_fb_obj_flush(obj, ORIGIN_CPU);
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}
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static void i915_clflush_work(struct work_struct *work)
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{
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struct clflush *clflush = container_of(work, typeof(*clflush), work);
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struct drm_i915_gem_object *obj = clflush->obj;
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if (i915_gem_object_pin_pages(obj)) {
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DRM_ERROR("Failed to acquire obj->pages for clflushing\n");
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goto out;
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}
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__i915_do_clflush(obj);
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i915_gem_object_unpin_pages(obj);
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out:
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i915_gem_object_put(obj);
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dma_fence_signal(&clflush->dma);
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dma_fence_put(&clflush->dma);
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}
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static int __i915_sw_fence_call
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i915_clflush_notify(struct i915_sw_fence *fence,
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enum i915_sw_fence_notify state)
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{
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struct clflush *clflush = container_of(fence, typeof(*clflush), wait);
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switch (state) {
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case FENCE_COMPLETE:
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schedule_work(&clflush->work);
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break;
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case FENCE_FREE:
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dma_fence_put(&clflush->dma);
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break;
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}
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return NOTIFY_DONE;
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}
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bool i915_gem_clflush_object(struct drm_i915_gem_object *obj,
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unsigned int flags)
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{
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struct clflush *clflush;
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/*
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* Stolen memory is always coherent with the GPU as it is explicitly
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* marked as wc by the system, or the system is cache-coherent.
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* Similarly, we only access struct pages through the CPU cache, so
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* anything not backed by physical memory we consider to be always
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* coherent and not need clflushing.
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*/
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if (!i915_gem_object_has_struct_page(obj)) {
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obj->cache_dirty = false;
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return false;
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}
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/* If the GPU is snooping the contents of the CPU cache,
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* we do not need to manually clear the CPU cache lines. However,
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* the caches are only snooped when the render cache is
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* flushed/invalidated. As we always have to emit invalidations
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* and flushes when moving into and out of the RENDER domain, correct
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* snooping behaviour occurs naturally as the result of our domain
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* tracking.
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*/
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if (!(flags & I915_CLFLUSH_FORCE) &&
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obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)
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return false;
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trace_i915_gem_object_clflush(obj);
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clflush = NULL;
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if (!(flags & I915_CLFLUSH_SYNC))
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clflush = kmalloc(sizeof(*clflush), GFP_KERNEL);
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if (clflush) {
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GEM_BUG_ON(!obj->cache_dirty);
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dma_fence_init(&clflush->dma,
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&i915_clflush_ops,
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&clflush_lock,
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to_i915(obj->base.dev)->mm.unordered_timeline,
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0);
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i915_sw_fence_init(&clflush->wait, i915_clflush_notify);
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clflush->obj = i915_gem_object_get(obj);
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INIT_WORK(&clflush->work, i915_clflush_work);
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dma_fence_get(&clflush->dma);
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i915_sw_fence_await_reservation(&clflush->wait,
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obj->resv, NULL,
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true, I915_FENCE_TIMEOUT,
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I915_FENCE_GFP);
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reservation_object_lock(obj->resv, NULL);
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reservation_object_add_excl_fence(obj->resv, &clflush->dma);
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reservation_object_unlock(obj->resv);
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i915_sw_fence_commit(&clflush->wait);
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} else if (obj->mm.pages) {
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__i915_do_clflush(obj);
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} else {
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GEM_BUG_ON(obj->write_domain != I915_GEM_DOMAIN_CPU);
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}
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obj->cache_dirty = false;
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return true;
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}
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