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![Tvrtko Ursulin](/assets/img/avatar_default.png)
So far we have been relying on vm->file pointer being NULL to declare something GGTT. This has the unfortunate consequence that the default kernel context is also declared GGTT and interferes with the following patch which wants to instantiate VMA's and execute requests against the kernel context. Change the is_ggtt test to use an explicit flag in struct address_space to solve this issue. Note that the bit used is free since there is an alignment hole in the struct. v2: * Mark mock ggtt. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20180831143643.12366-1-tvrtko.ursulin@linux.intel.com
678 lines
20 KiB
C
678 lines
20 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Please try to maintain the following order within this file unless it makes
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* sense to do otherwise. From top to bottom:
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* 1. typedefs
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* 2. #defines, and macros
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* 3. structure definitions
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* 4. function prototypes
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*
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* Within each section, please try to order by generation in ascending order,
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* from top to bottom (ie. gen6 on the top, gen8 on the bottom).
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*/
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#ifndef __I915_GEM_GTT_H__
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#define __I915_GEM_GTT_H__
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#include <linux/io-mapping.h>
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#include <linux/mm.h>
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#include <linux/pagevec.h>
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#include "i915_request.h"
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#include "i915_selftest.h"
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#include "i915_timeline.h"
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#define I915_GTT_PAGE_SIZE_4K BIT(12)
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#define I915_GTT_PAGE_SIZE_64K BIT(16)
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#define I915_GTT_PAGE_SIZE_2M BIT(21)
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#define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K
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#define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M
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#define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE
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#define I915_FENCE_REG_NONE -1
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#define I915_MAX_NUM_FENCES 32
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/* 32 fences + sign bit for FENCE_REG_NONE */
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#define I915_MAX_NUM_FENCE_BITS 6
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struct drm_i915_file_private;
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struct drm_i915_fence_reg;
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struct i915_vma;
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typedef u32 gen6_pte_t;
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typedef u64 gen8_pte_t;
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typedef u64 gen8_pde_t;
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typedef u64 gen8_ppgtt_pdpe_t;
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typedef u64 gen8_ppgtt_pml4e_t;
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#define ggtt_total_entries(ggtt) ((ggtt)->vm.total >> PAGE_SHIFT)
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/* gen6-hsw has bit 11-4 for physical addr bit 39-32 */
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#define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
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#define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
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#define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
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#define GEN6_PTE_CACHE_LLC (2 << 1)
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#define GEN6_PTE_UNCACHED (1 << 1)
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#define GEN6_PTE_VALID (1 << 0)
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#define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len)))
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#define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1)
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#define I915_PDES 512
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#define I915_PDE_MASK (I915_PDES - 1)
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#define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT))
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#define GEN6_PTES I915_PTES(sizeof(gen6_pte_t))
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#define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE)
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#define GEN6_PD_ALIGN (PAGE_SIZE * 16)
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#define GEN6_PDE_SHIFT 22
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#define GEN6_PDE_VALID (1 << 0)
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#define GEN7_PTE_CACHE_L3_LLC (3 << 1)
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#define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2)
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#define BYT_PTE_WRITEABLE (1 << 1)
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/* Cacheability Control is a 4-bit value. The low three bits are stored in bits
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* 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
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*/
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#define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
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(((bits) & 0x8) << (11 - 3)))
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#define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
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#define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
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#define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
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#define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
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#define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
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#define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
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#define HSW_PTE_UNCACHED (0)
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#define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
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#define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
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/* GEN8 32b style address is defined as a 3 level page table:
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* 31:30 | 29:21 | 20:12 | 11:0
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* PDPE | PDE | PTE | offset
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* The difference as compared to normal x86 3 level page table is the PDPEs are
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* programmed via register.
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*/
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#define GEN8_3LVL_PDPES 4
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#define GEN8_PDE_SHIFT 21
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#define GEN8_PDE_MASK 0x1ff
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#define GEN8_PTE_SHIFT 12
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#define GEN8_PTE_MASK 0x1ff
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#define GEN8_PTES I915_PTES(sizeof(gen8_pte_t))
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/* GEN8 48b style address is defined as a 4 level page table:
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* 47:39 | 38:30 | 29:21 | 20:12 | 11:0
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* PML4E | PDPE | PDE | PTE | offset
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*/
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#define GEN8_PML4ES_PER_PML4 512
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#define GEN8_PML4E_SHIFT 39
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#define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1)
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#define GEN8_PDPE_SHIFT 30
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/* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page
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* tables */
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#define GEN8_PDPE_MASK 0x1ff
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#define PPAT_UNCACHED (_PAGE_PWT | _PAGE_PCD)
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#define PPAT_CACHED_PDE 0 /* WB LLC */
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#define PPAT_CACHED _PAGE_PAT /* WB LLCeLLC */
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#define PPAT_DISPLAY_ELLC _PAGE_PCD /* WT eLLC */
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#define CHV_PPAT_SNOOP (1<<6)
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#define GEN8_PPAT_AGE(x) ((x)<<4)
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#define GEN8_PPAT_LLCeLLC (3<<2)
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#define GEN8_PPAT_LLCELLC (2<<2)
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#define GEN8_PPAT_LLC (1<<2)
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#define GEN8_PPAT_WB (3<<0)
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#define GEN8_PPAT_WT (2<<0)
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#define GEN8_PPAT_WC (1<<0)
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#define GEN8_PPAT_UC (0<<0)
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#define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
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#define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8))
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#define GEN8_PPAT_GET_CA(x) ((x) & 3)
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#define GEN8_PPAT_GET_TC(x) ((x) & (3 << 2))
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#define GEN8_PPAT_GET_AGE(x) ((x) & (3 << 4))
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#define CHV_PPAT_GET_SNOOP(x) ((x) & (1 << 6))
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#define GEN8_PDE_IPS_64K BIT(11)
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#define GEN8_PDE_PS_2M BIT(7)
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struct sg_table;
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struct intel_rotation_info {
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struct intel_rotation_plane_info {
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/* tiles */
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unsigned int width, height, stride, offset;
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} plane[2];
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} __packed;
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struct intel_partial_info {
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u64 offset;
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unsigned int size;
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} __packed;
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enum i915_ggtt_view_type {
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I915_GGTT_VIEW_NORMAL = 0,
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I915_GGTT_VIEW_ROTATED = sizeof(struct intel_rotation_info),
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I915_GGTT_VIEW_PARTIAL = sizeof(struct intel_partial_info),
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};
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static inline void assert_i915_gem_gtt_types(void)
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{
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BUILD_BUG_ON(sizeof(struct intel_rotation_info) != 8*sizeof(unsigned int));
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BUILD_BUG_ON(sizeof(struct intel_partial_info) != sizeof(u64) + sizeof(unsigned int));
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/* As we encode the size of each branch inside the union into its type,
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* we have to be careful that each branch has a unique size.
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*/
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switch ((enum i915_ggtt_view_type)0) {
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case I915_GGTT_VIEW_NORMAL:
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case I915_GGTT_VIEW_PARTIAL:
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case I915_GGTT_VIEW_ROTATED:
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/* gcc complains if these are identical cases */
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break;
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}
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}
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struct i915_ggtt_view {
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enum i915_ggtt_view_type type;
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union {
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/* Members need to contain no holes/padding */
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struct intel_partial_info partial;
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struct intel_rotation_info rotated;
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};
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};
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enum i915_cache_level;
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struct i915_vma;
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struct i915_page_dma {
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struct page *page;
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int order;
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union {
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dma_addr_t daddr;
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/* For gen6/gen7 only. This is the offset in the GGTT
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* where the page directory entries for PPGTT begin
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*/
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u32 ggtt_offset;
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};
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};
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#define px_base(px) (&(px)->base)
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#define px_dma(px) (px_base(px)->daddr)
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struct i915_page_table {
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struct i915_page_dma base;
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unsigned int used_ptes;
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};
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struct i915_page_directory {
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struct i915_page_dma base;
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struct i915_page_table *page_table[I915_PDES]; /* PDEs */
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unsigned int used_pdes;
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};
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struct i915_page_directory_pointer {
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struct i915_page_dma base;
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struct i915_page_directory **page_directory;
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unsigned int used_pdpes;
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};
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struct i915_pml4 {
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struct i915_page_dma base;
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struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4];
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};
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struct i915_vma_ops {
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/* Map an object into an address space with the given cache flags. */
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int (*bind_vma)(struct i915_vma *vma,
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enum i915_cache_level cache_level,
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u32 flags);
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/*
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* Unmap an object from an address space. This usually consists of
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* setting the valid PTE entries to a reserved scratch page.
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*/
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void (*unbind_vma)(struct i915_vma *vma);
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int (*set_pages)(struct i915_vma *vma);
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void (*clear_pages)(struct i915_vma *vma);
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};
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struct pagestash {
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spinlock_t lock;
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struct pagevec pvec;
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};
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struct i915_address_space {
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struct drm_mm mm;
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struct drm_i915_private *i915;
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struct device *dma;
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/* Every address space belongs to a struct file - except for the global
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* GTT that is owned by the driver (and so @file is set to NULL). In
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* principle, no information should leak from one context to another
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* (or between files/processes etc) unless explicitly shared by the
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* owner. Tracking the owner is important in order to free up per-file
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* objects along with the file, to aide resource tracking, and to
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* assign blame.
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*/
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struct drm_i915_file_private *file;
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u64 total; /* size addr space maps (ex. 2GB for ggtt) */
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u64 reserved; /* size addr space reserved */
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bool closed;
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struct mutex mutex; /* protects vma and our lists */
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struct i915_page_dma scratch_page;
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struct i915_page_table *scratch_pt;
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struct i915_page_directory *scratch_pd;
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struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */
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/**
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* List of objects currently involved in rendering.
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*
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* Includes buffers having the contents of their GPU caches
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* flushed, not necessarily primitives. last_read_req
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* represents when the rendering involved will be completed.
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*
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* A reference is held on the buffer while on this list.
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*/
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struct list_head active_list;
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/**
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* LRU list of objects which are not in the ringbuffer and
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* are ready to unbind, but are still in the GTT.
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*
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* last_read_req is NULL while an object is in this list.
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*
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* A reference is not held on the buffer while on this list,
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* as merely being GTT-bound shouldn't prevent its being
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* freed, and we'll pull it off the list in the free path.
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*/
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struct list_head inactive_list;
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/**
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* List of vma that have been unbound.
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*
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* A reference is not held on the buffer while on this list.
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*/
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struct list_head unbound_list;
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struct pagestash free_pages;
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/* Global GTT */
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bool is_ggtt:1;
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/* Some systems require uncached updates of the page directories */
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bool pt_kmap_wc:1;
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/* Some systems support read-only mappings for GGTT and/or PPGTT */
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bool has_read_only:1;
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/* FIXME: Need a more generic return type */
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gen6_pte_t (*pte_encode)(dma_addr_t addr,
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enum i915_cache_level level,
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u32 flags); /* Create a valid PTE */
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/* flags for pte_encode */
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#define PTE_READ_ONLY (1<<0)
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int (*allocate_va_range)(struct i915_address_space *vm,
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u64 start, u64 length);
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void (*clear_range)(struct i915_address_space *vm,
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u64 start, u64 length);
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void (*insert_page)(struct i915_address_space *vm,
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dma_addr_t addr,
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u64 offset,
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enum i915_cache_level cache_level,
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u32 flags);
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void (*insert_entries)(struct i915_address_space *vm,
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struct i915_vma *vma,
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enum i915_cache_level cache_level,
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u32 flags);
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void (*cleanup)(struct i915_address_space *vm);
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struct i915_vma_ops vma_ops;
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I915_SELFTEST_DECLARE(struct fault_attr fault_attr);
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I915_SELFTEST_DECLARE(bool scrub_64K);
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};
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#define i915_is_ggtt(vm) ((vm)->is_ggtt)
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static inline bool
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i915_vm_is_48bit(const struct i915_address_space *vm)
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{
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return (vm->total - 1) >> 32;
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}
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static inline bool
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i915_vm_has_scratch_64K(struct i915_address_space *vm)
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{
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return vm->scratch_page.order == get_order(I915_GTT_PAGE_SIZE_64K);
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}
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/* The Graphics Translation Table is the way in which GEN hardware translates a
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* Graphics Virtual Address into a Physical Address. In addition to the normal
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* collateral associated with any va->pa translations GEN hardware also has a
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* portion of the GTT which can be mapped by the CPU and remain both coherent
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* and correct (in cases like swizzling). That region is referred to as GMADR in
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* the spec.
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*/
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struct i915_ggtt {
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struct i915_address_space vm;
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struct io_mapping iomap; /* Mapping to our CPU mappable region */
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struct resource gmadr; /* GMADR resource */
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resource_size_t mappable_end; /* End offset that we can CPU map */
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/** "Graphics Stolen Memory" holds the global PTEs */
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void __iomem *gsm;
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void (*invalidate)(struct drm_i915_private *dev_priv);
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bool do_idle_maps;
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int mtrr;
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u32 pin_bias;
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struct drm_mm_node error_capture;
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};
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struct i915_hw_ppgtt {
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struct i915_address_space vm;
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struct kref ref;
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unsigned long pd_dirty_rings;
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union {
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struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */
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struct i915_page_directory_pointer pdp; /* GEN8+ */
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struct i915_page_directory pd; /* GEN6-7 */
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};
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void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m);
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};
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struct gen6_hw_ppgtt {
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struct i915_hw_ppgtt base;
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struct i915_vma *vma;
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gen6_pte_t __iomem *pd_addr;
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gen6_pte_t scratch_pte;
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unsigned int pin_count;
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bool scan_for_unused_pt;
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};
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#define __to_gen6_ppgtt(base) container_of(base, struct gen6_hw_ppgtt, base)
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static inline struct gen6_hw_ppgtt *to_gen6_ppgtt(struct i915_hw_ppgtt *base)
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{
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BUILD_BUG_ON(offsetof(struct gen6_hw_ppgtt, base));
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return __to_gen6_ppgtt(base);
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}
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/*
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* gen6_for_each_pde() iterates over every pde from start until start+length.
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* If start and start+length are not perfectly divisible, the macro will round
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* down and up as needed. Start=0 and length=2G effectively iterates over
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* every PDE in the system. The macro modifies ALL its parameters except 'pd',
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* so each of the other parameters should preferably be a simple variable, or
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* at most an lvalue with no side-effects!
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*/
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#define gen6_for_each_pde(pt, pd, start, length, iter) \
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for (iter = gen6_pde_index(start); \
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length > 0 && iter < I915_PDES && \
|
|
(pt = (pd)->page_table[iter], true); \
|
|
({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \
|
|
temp = min(temp - start, length); \
|
|
start += temp, length -= temp; }), ++iter)
|
|
|
|
#define gen6_for_all_pdes(pt, pd, iter) \
|
|
for (iter = 0; \
|
|
iter < I915_PDES && \
|
|
(pt = (pd)->page_table[iter], true); \
|
|
++iter)
|
|
|
|
static inline u32 i915_pte_index(u64 address, unsigned int pde_shift)
|
|
{
|
|
const u32 mask = NUM_PTE(pde_shift) - 1;
|
|
|
|
return (address >> PAGE_SHIFT) & mask;
|
|
}
|
|
|
|
/* Helper to counts the number of PTEs within the given length. This count
|
|
* does not cross a page table boundary, so the max value would be
|
|
* GEN6_PTES for GEN6, and GEN8_PTES for GEN8.
|
|
*/
|
|
static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift)
|
|
{
|
|
const u64 mask = ~((1ULL << pde_shift) - 1);
|
|
u64 end;
|
|
|
|
GEM_BUG_ON(length == 0);
|
|
GEM_BUG_ON(offset_in_page(addr | length));
|
|
|
|
end = addr + length;
|
|
|
|
if ((addr & mask) != (end & mask))
|
|
return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift);
|
|
|
|
return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift);
|
|
}
|
|
|
|
static inline u32 i915_pde_index(u64 addr, u32 shift)
|
|
{
|
|
return (addr >> shift) & I915_PDE_MASK;
|
|
}
|
|
|
|
static inline u32 gen6_pte_index(u32 addr)
|
|
{
|
|
return i915_pte_index(addr, GEN6_PDE_SHIFT);
|
|
}
|
|
|
|
static inline u32 gen6_pte_count(u32 addr, u32 length)
|
|
{
|
|
return i915_pte_count(addr, length, GEN6_PDE_SHIFT);
|
|
}
|
|
|
|
static inline u32 gen6_pde_index(u32 addr)
|
|
{
|
|
return i915_pde_index(addr, GEN6_PDE_SHIFT);
|
|
}
|
|
|
|
static inline unsigned int
|
|
i915_pdpes_per_pdp(const struct i915_address_space *vm)
|
|
{
|
|
if (i915_vm_is_48bit(vm))
|
|
return GEN8_PML4ES_PER_PML4;
|
|
|
|
return GEN8_3LVL_PDPES;
|
|
}
|
|
|
|
/* Equivalent to the gen6 version, For each pde iterates over every pde
|
|
* between from start until start + length. On gen8+ it simply iterates
|
|
* over every page directory entry in a page directory.
|
|
*/
|
|
#define gen8_for_each_pde(pt, pd, start, length, iter) \
|
|
for (iter = gen8_pde_index(start); \
|
|
length > 0 && iter < I915_PDES && \
|
|
(pt = (pd)->page_table[iter], true); \
|
|
({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \
|
|
temp = min(temp - start, length); \
|
|
start += temp, length -= temp; }), ++iter)
|
|
|
|
#define gen8_for_each_pdpe(pd, pdp, start, length, iter) \
|
|
for (iter = gen8_pdpe_index(start); \
|
|
length > 0 && iter < i915_pdpes_per_pdp(vm) && \
|
|
(pd = (pdp)->page_directory[iter], true); \
|
|
({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \
|
|
temp = min(temp - start, length); \
|
|
start += temp, length -= temp; }), ++iter)
|
|
|
|
#define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \
|
|
for (iter = gen8_pml4e_index(start); \
|
|
length > 0 && iter < GEN8_PML4ES_PER_PML4 && \
|
|
(pdp = (pml4)->pdps[iter], true); \
|
|
({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \
|
|
temp = min(temp - start, length); \
|
|
start += temp, length -= temp; }), ++iter)
|
|
|
|
static inline u32 gen8_pte_index(u64 address)
|
|
{
|
|
return i915_pte_index(address, GEN8_PDE_SHIFT);
|
|
}
|
|
|
|
static inline u32 gen8_pde_index(u64 address)
|
|
{
|
|
return i915_pde_index(address, GEN8_PDE_SHIFT);
|
|
}
|
|
|
|
static inline u32 gen8_pdpe_index(u64 address)
|
|
{
|
|
return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK;
|
|
}
|
|
|
|
static inline u32 gen8_pml4e_index(u64 address)
|
|
{
|
|
return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK;
|
|
}
|
|
|
|
static inline u64 gen8_pte_count(u64 address, u64 length)
|
|
{
|
|
return i915_pte_count(address, length, GEN8_PDE_SHIFT);
|
|
}
|
|
|
|
static inline dma_addr_t
|
|
i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n)
|
|
{
|
|
return px_dma(ppgtt->pdp.page_directory[n]);
|
|
}
|
|
|
|
static inline struct i915_ggtt *
|
|
i915_vm_to_ggtt(struct i915_address_space *vm)
|
|
{
|
|
GEM_BUG_ON(!i915_is_ggtt(vm));
|
|
return container_of(vm, struct i915_ggtt, vm);
|
|
}
|
|
|
|
#define INTEL_MAX_PPAT_ENTRIES 8
|
|
#define INTEL_PPAT_PERFECT_MATCH (~0U)
|
|
|
|
struct intel_ppat;
|
|
|
|
struct intel_ppat_entry {
|
|
struct intel_ppat *ppat;
|
|
struct kref ref;
|
|
u8 value;
|
|
};
|
|
|
|
struct intel_ppat {
|
|
struct intel_ppat_entry entries[INTEL_MAX_PPAT_ENTRIES];
|
|
DECLARE_BITMAP(used, INTEL_MAX_PPAT_ENTRIES);
|
|
DECLARE_BITMAP(dirty, INTEL_MAX_PPAT_ENTRIES);
|
|
unsigned int max_entries;
|
|
u8 clear_value;
|
|
/*
|
|
* Return a score to show how two PPAT values match,
|
|
* a INTEL_PPAT_PERFECT_MATCH indicates a perfect match
|
|
*/
|
|
unsigned int (*match)(u8 src, u8 dst);
|
|
void (*update_hw)(struct drm_i915_private *i915);
|
|
|
|
struct drm_i915_private *i915;
|
|
};
|
|
|
|
const struct intel_ppat_entry *
|
|
intel_ppat_get(struct drm_i915_private *i915, u8 value);
|
|
void intel_ppat_put(const struct intel_ppat_entry *entry);
|
|
|
|
int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915);
|
|
void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915);
|
|
|
|
int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv);
|
|
int i915_ggtt_init_hw(struct drm_i915_private *dev_priv);
|
|
int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv);
|
|
void i915_ggtt_enable_guc(struct drm_i915_private *i915);
|
|
void i915_ggtt_disable_guc(struct drm_i915_private *i915);
|
|
int i915_gem_init_ggtt(struct drm_i915_private *dev_priv);
|
|
void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv);
|
|
|
|
int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv);
|
|
void i915_ppgtt_release(struct kref *kref);
|
|
struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv,
|
|
struct drm_i915_file_private *fpriv);
|
|
void i915_ppgtt_close(struct i915_address_space *vm);
|
|
static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt)
|
|
{
|
|
if (ppgtt)
|
|
kref_get(&ppgtt->ref);
|
|
}
|
|
static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt)
|
|
{
|
|
if (ppgtt)
|
|
kref_put(&ppgtt->ref, i915_ppgtt_release);
|
|
}
|
|
|
|
int gen6_ppgtt_pin(struct i915_hw_ppgtt *base);
|
|
void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base);
|
|
|
|
void i915_check_and_clear_faults(struct drm_i915_private *dev_priv);
|
|
void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv);
|
|
void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv);
|
|
|
|
int __must_check i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj,
|
|
struct sg_table *pages);
|
|
void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj,
|
|
struct sg_table *pages);
|
|
|
|
int i915_gem_gtt_reserve(struct i915_address_space *vm,
|
|
struct drm_mm_node *node,
|
|
u64 size, u64 offset, unsigned long color,
|
|
unsigned int flags);
|
|
|
|
int i915_gem_gtt_insert(struct i915_address_space *vm,
|
|
struct drm_mm_node *node,
|
|
u64 size, u64 alignment, unsigned long color,
|
|
u64 start, u64 end, unsigned int flags);
|
|
|
|
/* Flags used by pin/bind&friends. */
|
|
#define PIN_NONBLOCK BIT(0)
|
|
#define PIN_MAPPABLE BIT(1)
|
|
#define PIN_ZONE_4G BIT(2)
|
|
#define PIN_NONFAULT BIT(3)
|
|
#define PIN_NOEVICT BIT(4)
|
|
|
|
#define PIN_MBZ BIT(5) /* I915_VMA_PIN_OVERFLOW */
|
|
#define PIN_GLOBAL BIT(6) /* I915_VMA_GLOBAL_BIND */
|
|
#define PIN_USER BIT(7) /* I915_VMA_LOCAL_BIND */
|
|
#define PIN_UPDATE BIT(8)
|
|
|
|
#define PIN_HIGH BIT(9)
|
|
#define PIN_OFFSET_BIAS BIT(10)
|
|
#define PIN_OFFSET_FIXED BIT(11)
|
|
#define PIN_OFFSET_MASK (-I915_GTT_PAGE_SIZE)
|
|
|
|
#endif
|