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![Imre Deak](/assets/img/avatar_default.png)
On GLK sporadic timeouts occur during PHY0 enabling. Based on logs it looks like they happen sometime after a system suspend/resume cycle, with the same power well enabling succeeding both before and after the failed one and no other problems observed. The current timeout in the code is not actually specified by BSpec, so let's try to increase that until a BSpec update. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105771 Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180409122716.4055-1-imre.deak@intel.com Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
1080 lines
32 KiB
C
1080 lines
32 KiB
C
/*
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* Copyright © 2014-2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "intel_drv.h"
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/**
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* DOC: DPIO
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*
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* VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
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* ports. DPIO is the name given to such a display PHY. These PHYs
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* don't follow the standard programming model using direct MMIO
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* registers, and instead their registers must be accessed trough IOSF
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* sideband. VLV has one such PHY for driving ports B and C, and CHV
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* adds another PHY for driving port D. Each PHY responds to specific
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* IOSF-SB port.
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*
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* Each display PHY is made up of one or two channels. Each channel
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* houses a common lane part which contains the PLL and other common
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* logic. CH0 common lane also contains the IOSF-SB logic for the
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* Common Register Interface (CRI) ie. the DPIO registers. CRI clock
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* must be running when any DPIO registers are accessed.
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*
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* In addition to having their own registers, the PHYs are also
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* controlled through some dedicated signals from the display
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* controller. These include PLL reference clock enable, PLL enable,
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* and CRI clock selection, for example.
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*
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* Eeach channel also has two splines (also called data lanes), and
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* each spline is made up of one Physical Access Coding Sub-Layer
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* (PCS) block and two TX lanes. So each channel has two PCS blocks
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* and four TX lanes. The TX lanes are used as DP lanes or TMDS
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* data/clock pairs depending on the output type.
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*
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* Additionally the PHY also contains an AUX lane with AUX blocks
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* for each channel. This is used for DP AUX communication, but
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* this fact isn't really relevant for the driver since AUX is
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* controlled from the display controller side. No DPIO registers
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* need to be accessed during AUX communication,
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*
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* Generally on VLV/CHV the common lane corresponds to the pipe and
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* the spline (PCS/TX) corresponds to the port.
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*
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* For dual channel PHY (VLV/CHV):
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*
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* pipe A == CMN/PLL/REF CH0
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*
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* pipe B == CMN/PLL/REF CH1
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*
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* port B == PCS/TX CH0
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*
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* port C == PCS/TX CH1
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*
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* This is especially important when we cross the streams
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* ie. drive port B with pipe B, or port C with pipe A.
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*
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* For single channel PHY (CHV):
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*
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* pipe C == CMN/PLL/REF CH0
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*
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* port D == PCS/TX CH0
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*
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* On BXT the entire PHY channel corresponds to the port. That means
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* the PLL is also now associated with the port rather than the pipe,
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* and so the clock needs to be routed to the appropriate transcoder.
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* Port A PLL is directly connected to transcoder EDP and port B/C
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* PLLs can be routed to any transcoder A/B/C.
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*
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* Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
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* digital port D (CHV) or port A (BXT). ::
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*
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*
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* Dual channel PHY (VLV/CHV/BXT)
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* ---------------------------------
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* | CH0 | CH1 |
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* | CMN/PLL/REF | CMN/PLL/REF |
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* |---------------|---------------| Display PHY
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* | PCS01 | PCS23 | PCS01 | PCS23 |
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* |-------|-------|-------|-------|
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* |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
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* ---------------------------------
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* | DDI0 | DDI1 | DP/HDMI ports
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* ---------------------------------
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*
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* Single channel PHY (CHV/BXT)
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* -----------------
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* | CH0 |
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* | CMN/PLL/REF |
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* |---------------| Display PHY
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* | PCS01 | PCS23 |
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* |-------|-------|
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* |TX0|TX1|TX2|TX3|
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* -----------------
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* | DDI2 | DP/HDMI port
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* -----------------
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*/
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/**
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* struct bxt_ddi_phy_info - Hold info for a broxton DDI phy
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*/
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struct bxt_ddi_phy_info {
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/**
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* @dual_channel: true if this phy has a second channel.
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*/
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bool dual_channel;
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/**
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* @rcomp_phy: If -1, indicates this phy has its own rcomp resistor.
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* Otherwise the GRC value will be copied from the phy indicated by
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* this field.
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*/
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enum dpio_phy rcomp_phy;
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/**
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* @reset_delay: delay in us to wait before setting the common reset
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* bit in BXT_PHY_CTL_FAMILY, which effectively enables the phy.
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*/
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int reset_delay;
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/**
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* @pwron_mask: Mask with the appropriate bit set that would cause the
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* punit to power this phy if written to BXT_P_CR_GT_DISP_PWRON.
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*/
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u32 pwron_mask;
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/**
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* @channel: struct containing per channel information.
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*/
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struct {
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/**
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* @channel.port: which port maps to this channel.
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*/
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enum port port;
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} channel[2];
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};
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static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
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[DPIO_PHY0] = {
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.dual_channel = true,
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.rcomp_phy = DPIO_PHY1,
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.pwron_mask = BIT(0),
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.channel = {
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[DPIO_CH0] = { .port = PORT_B },
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[DPIO_CH1] = { .port = PORT_C },
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}
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},
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[DPIO_PHY1] = {
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.dual_channel = false,
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.rcomp_phy = -1,
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.pwron_mask = BIT(1),
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.channel = {
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[DPIO_CH0] = { .port = PORT_A },
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}
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},
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};
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static const struct bxt_ddi_phy_info glk_ddi_phy_info[] = {
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[DPIO_PHY0] = {
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.dual_channel = false,
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.rcomp_phy = DPIO_PHY1,
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.pwron_mask = BIT(0),
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.reset_delay = 20,
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.channel = {
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[DPIO_CH0] = { .port = PORT_B },
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}
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},
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[DPIO_PHY1] = {
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.dual_channel = false,
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.rcomp_phy = -1,
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.pwron_mask = BIT(3),
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.reset_delay = 20,
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.channel = {
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[DPIO_CH0] = { .port = PORT_A },
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}
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},
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[DPIO_PHY2] = {
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.dual_channel = false,
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.rcomp_phy = DPIO_PHY1,
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.pwron_mask = BIT(1),
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.reset_delay = 20,
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.channel = {
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[DPIO_CH0] = { .port = PORT_C },
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}
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},
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};
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static const struct bxt_ddi_phy_info *
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bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count)
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{
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if (IS_GEMINILAKE(dev_priv)) {
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*count = ARRAY_SIZE(glk_ddi_phy_info);
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return glk_ddi_phy_info;
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} else {
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*count = ARRAY_SIZE(bxt_ddi_phy_info);
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return bxt_ddi_phy_info;
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}
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}
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static const struct bxt_ddi_phy_info *
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bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy)
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{
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int count;
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const struct bxt_ddi_phy_info *phy_list =
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bxt_get_phy_list(dev_priv, &count);
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return &phy_list[phy];
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}
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void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
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enum dpio_phy *phy, enum dpio_channel *ch)
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{
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const struct bxt_ddi_phy_info *phy_info, *phys;
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int i, count;
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phys = bxt_get_phy_list(dev_priv, &count);
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for (i = 0; i < count; i++) {
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phy_info = &phys[i];
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if (port == phy_info->channel[DPIO_CH0].port) {
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*phy = i;
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*ch = DPIO_CH0;
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return;
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}
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if (phy_info->dual_channel &&
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port == phy_info->channel[DPIO_CH1].port) {
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*phy = i;
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*ch = DPIO_CH1;
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return;
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}
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}
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WARN(1, "PHY not found for PORT %c", port_name(port));
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*phy = DPIO_PHY0;
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*ch = DPIO_CH0;
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}
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void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
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enum port port, u32 margin, u32 scale,
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u32 enable, u32 deemphasis)
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{
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u32 val;
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enum dpio_phy phy;
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enum dpio_channel ch;
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bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
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/*
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* While we write to the group register to program all lanes at once we
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* can read only lane registers and we pick lanes 0/1 for that.
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*/
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val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch));
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val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
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I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val);
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val = I915_READ(BXT_PORT_TX_DW2_LN0(phy, ch));
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val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
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val |= margin << MARGIN_000_SHIFT | scale << UNIQ_TRANS_SCALE_SHIFT;
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I915_WRITE(BXT_PORT_TX_DW2_GRP(phy, ch), val);
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val = I915_READ(BXT_PORT_TX_DW3_LN0(phy, ch));
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val &= ~SCALE_DCOMP_METHOD;
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if (enable)
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val |= SCALE_DCOMP_METHOD;
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if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
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DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
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I915_WRITE(BXT_PORT_TX_DW3_GRP(phy, ch), val);
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val = I915_READ(BXT_PORT_TX_DW4_LN0(phy, ch));
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val &= ~DE_EMPHASIS;
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val |= deemphasis << DEEMPH_SHIFT;
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I915_WRITE(BXT_PORT_TX_DW4_GRP(phy, ch), val);
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val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch));
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val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
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I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val);
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}
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bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
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enum dpio_phy phy)
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{
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const struct bxt_ddi_phy_info *phy_info;
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phy_info = bxt_get_phy_info(dev_priv, phy);
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if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))
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return false;
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if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
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(PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
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DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n",
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phy);
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return false;
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}
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if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
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DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n",
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phy);
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return false;
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}
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return true;
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}
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static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
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{
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u32 val = I915_READ(BXT_PORT_REF_DW6(phy));
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return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
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}
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static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
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enum dpio_phy phy)
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{
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if (intel_wait_for_register(dev_priv,
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BXT_PORT_REF_DW3(phy),
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GRC_DONE, GRC_DONE,
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10))
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DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
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}
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static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
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enum dpio_phy phy)
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{
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const struct bxt_ddi_phy_info *phy_info;
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u32 val;
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phy_info = bxt_get_phy_info(dev_priv, phy);
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if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
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/* Still read out the GRC value for state verification */
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if (phy_info->rcomp_phy != -1)
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dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
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if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
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DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
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"won't reprogram it\n", phy);
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return;
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}
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DRM_DEBUG_DRIVER("DDI PHY %d enabled with invalid state, "
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"force reprogramming it\n", phy);
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}
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val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
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val |= phy_info->pwron_mask;
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I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
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/*
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* The PHY registers start out inaccessible and respond to reads with
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* all 1s. Eventually they become accessible as they power up, then
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* the reserved bit will give the default 0. Poll on the reserved bit
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* becoming 0 to find when the PHY is accessible.
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* The flag should get set in 100us according to the HW team, but
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* use 1ms due to occasional timeouts observed with that.
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*/
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if (intel_wait_for_register_fw(dev_priv, BXT_PORT_CL1CM_DW0(phy),
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PHY_RESERVED | PHY_POWER_GOOD,
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PHY_POWER_GOOD,
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1))
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DRM_ERROR("timeout during PHY%d power on\n", phy);
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/* Program PLL Rcomp code offset */
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val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
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val &= ~IREF0RC_OFFSET_MASK;
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val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
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I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
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val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
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val &= ~IREF1RC_OFFSET_MASK;
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val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
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I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
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/* Program power gating */
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val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
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val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
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SUS_CLK_CONFIG;
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I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
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if (phy_info->dual_channel) {
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val = I915_READ(BXT_PORT_CL2CM_DW6(phy));
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val |= DW6_OLDO_DYN_PWR_DOWN_EN;
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I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val);
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}
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if (phy_info->rcomp_phy != -1) {
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uint32_t grc_code;
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bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy);
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/*
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* PHY0 isn't connected to an RCOMP resistor so copy over
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* the corresponding calibrated value from PHY1, and disable
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* the automatic calibration on PHY0.
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*/
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val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv,
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phy_info->rcomp_phy);
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grc_code = val << GRC_CODE_FAST_SHIFT |
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val << GRC_CODE_SLOW_SHIFT |
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val;
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I915_WRITE(BXT_PORT_REF_DW6(phy), grc_code);
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val = I915_READ(BXT_PORT_REF_DW8(phy));
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val |= GRC_DIS | GRC_RDY_OVRD;
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I915_WRITE(BXT_PORT_REF_DW8(phy), val);
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}
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if (phy_info->reset_delay)
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udelay(phy_info->reset_delay);
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val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
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val |= COMMON_RESET_DIS;
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I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
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}
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void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
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{
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const struct bxt_ddi_phy_info *phy_info;
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uint32_t val;
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phy_info = bxt_get_phy_info(dev_priv, phy);
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val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
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val &= ~COMMON_RESET_DIS;
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I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
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val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
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val &= ~phy_info->pwron_mask;
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I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
|
|
}
|
|
|
|
void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
|
|
{
|
|
const struct bxt_ddi_phy_info *phy_info =
|
|
bxt_get_phy_info(dev_priv, phy);
|
|
enum dpio_phy rcomp_phy = phy_info->rcomp_phy;
|
|
bool was_enabled;
|
|
|
|
lockdep_assert_held(&dev_priv->power_domains.lock);
|
|
|
|
was_enabled = true;
|
|
if (rcomp_phy != -1)
|
|
was_enabled = bxt_ddi_phy_is_enabled(dev_priv, rcomp_phy);
|
|
|
|
/*
|
|
* We need to copy the GRC calibration value from rcomp_phy,
|
|
* so make sure it's powered up.
|
|
*/
|
|
if (!was_enabled)
|
|
_bxt_ddi_phy_init(dev_priv, rcomp_phy);
|
|
|
|
_bxt_ddi_phy_init(dev_priv, phy);
|
|
|
|
if (!was_enabled)
|
|
bxt_ddi_phy_uninit(dev_priv, rcomp_phy);
|
|
}
|
|
|
|
static bool __printf(6, 7)
|
|
__phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
|
|
i915_reg_t reg, u32 mask, u32 expected,
|
|
const char *reg_fmt, ...)
|
|
{
|
|
struct va_format vaf;
|
|
va_list args;
|
|
u32 val;
|
|
|
|
val = I915_READ(reg);
|
|
if ((val & mask) == expected)
|
|
return true;
|
|
|
|
va_start(args, reg_fmt);
|
|
vaf.fmt = reg_fmt;
|
|
vaf.va = &args;
|
|
|
|
DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: "
|
|
"current %08x, expected %08x (mask %08x)\n",
|
|
phy, &vaf, reg.reg, val, (val & ~mask) | expected,
|
|
mask);
|
|
|
|
va_end(args);
|
|
|
|
return false;
|
|
}
|
|
|
|
bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
|
|
enum dpio_phy phy)
|
|
{
|
|
const struct bxt_ddi_phy_info *phy_info;
|
|
uint32_t mask;
|
|
bool ok;
|
|
|
|
phy_info = bxt_get_phy_info(dev_priv, phy);
|
|
|
|
#define _CHK(reg, mask, exp, fmt, ...) \
|
|
__phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \
|
|
## __VA_ARGS__)
|
|
|
|
if (!bxt_ddi_phy_is_enabled(dev_priv, phy))
|
|
return false;
|
|
|
|
ok = true;
|
|
|
|
/* PLL Rcomp code offset */
|
|
ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
|
|
IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
|
|
"BXT_PORT_CL1CM_DW9(%d)", phy);
|
|
ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
|
|
IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
|
|
"BXT_PORT_CL1CM_DW10(%d)", phy);
|
|
|
|
/* Power gating */
|
|
mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
|
|
ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
|
|
"BXT_PORT_CL1CM_DW28(%d)", phy);
|
|
|
|
if (phy_info->dual_channel)
|
|
ok &= _CHK(BXT_PORT_CL2CM_DW6(phy),
|
|
DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
|
|
"BXT_PORT_CL2CM_DW6(%d)", phy);
|
|
|
|
if (phy_info->rcomp_phy != -1) {
|
|
u32 grc_code = dev_priv->bxt_phy_grc;
|
|
|
|
grc_code = grc_code << GRC_CODE_FAST_SHIFT |
|
|
grc_code << GRC_CODE_SLOW_SHIFT |
|
|
grc_code;
|
|
mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
|
|
GRC_CODE_NOM_MASK;
|
|
ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code,
|
|
"BXT_PORT_REF_DW6(%d)", phy);
|
|
|
|
mask = GRC_DIS | GRC_RDY_OVRD;
|
|
ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask,
|
|
"BXT_PORT_REF_DW8(%d)", phy);
|
|
}
|
|
|
|
return ok;
|
|
#undef _CHK
|
|
}
|
|
|
|
uint8_t
|
|
bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count)
|
|
{
|
|
switch (lane_count) {
|
|
case 1:
|
|
return 0;
|
|
case 2:
|
|
return BIT(2) | BIT(0);
|
|
case 4:
|
|
return BIT(3) | BIT(2) | BIT(0);
|
|
default:
|
|
MISSING_CASE(lane_count);
|
|
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
|
|
uint8_t lane_lat_optim_mask)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
enum port port = encoder->port;
|
|
enum dpio_phy phy;
|
|
enum dpio_channel ch;
|
|
int lane;
|
|
|
|
bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
|
|
|
|
for (lane = 0; lane < 4; lane++) {
|
|
u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane));
|
|
|
|
/*
|
|
* Note that on CHV this flag is called UPAR, but has
|
|
* the same function.
|
|
*/
|
|
val &= ~LATENCY_OPTIM;
|
|
if (lane_lat_optim_mask & BIT(lane))
|
|
val |= LATENCY_OPTIM;
|
|
|
|
I915_WRITE(BXT_PORT_TX_DW14_LN(phy, ch, lane), val);
|
|
}
|
|
}
|
|
|
|
uint8_t
|
|
bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
enum port port = encoder->port;
|
|
enum dpio_phy phy;
|
|
enum dpio_channel ch;
|
|
int lane;
|
|
uint8_t mask;
|
|
|
|
bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
|
|
|
|
mask = 0;
|
|
for (lane = 0; lane < 4; lane++) {
|
|
u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane));
|
|
|
|
if (val & LATENCY_OPTIM)
|
|
mask |= BIT(lane);
|
|
}
|
|
|
|
return mask;
|
|
}
|
|
|
|
|
|
void chv_set_phy_signal_level(struct intel_encoder *encoder,
|
|
u32 deemph_reg_value, u32 margin_reg_value,
|
|
bool uniq_trans_scale)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
|
|
enum dpio_channel ch = vlv_dport_to_channel(dport);
|
|
enum pipe pipe = intel_crtc->pipe;
|
|
u32 val;
|
|
int i;
|
|
|
|
mutex_lock(&dev_priv->sb_lock);
|
|
|
|
/* Clear calc init */
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
|
|
val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
|
|
val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
|
|
val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
|
|
|
|
if (intel_crtc->config->lane_count > 2) {
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
|
|
val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
|
|
val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
|
|
val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
|
|
}
|
|
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
|
|
val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
|
|
val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
|
|
|
|
if (intel_crtc->config->lane_count > 2) {
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
|
|
val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
|
|
val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
|
|
}
|
|
|
|
/* Program swing deemph */
|
|
for (i = 0; i < intel_crtc->config->lane_count; i++) {
|
|
val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
|
|
val &= ~DPIO_SWING_DEEMPH9P5_MASK;
|
|
val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
|
|
vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
|
|
}
|
|
|
|
/* Program swing margin */
|
|
for (i = 0; i < intel_crtc->config->lane_count; i++) {
|
|
val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
|
|
|
|
val &= ~DPIO_SWING_MARGIN000_MASK;
|
|
val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
|
|
|
|
/*
|
|
* Supposedly this value shouldn't matter when unique transition
|
|
* scale is disabled, but in fact it does matter. Let's just
|
|
* always program the same value and hope it's OK.
|
|
*/
|
|
val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
|
|
val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
|
|
|
|
vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
|
|
}
|
|
|
|
/*
|
|
* The document said it needs to set bit 27 for ch0 and bit 26
|
|
* for ch1. Might be a typo in the doc.
|
|
* For now, for this unique transition scale selection, set bit
|
|
* 27 for ch0 and ch1.
|
|
*/
|
|
for (i = 0; i < intel_crtc->config->lane_count; i++) {
|
|
val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
|
|
if (uniq_trans_scale)
|
|
val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
|
|
else
|
|
val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
|
|
vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
|
|
}
|
|
|
|
/* Start swing calculation */
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
|
|
val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
|
|
|
|
if (intel_crtc->config->lane_count > 2) {
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
|
|
val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
|
|
}
|
|
|
|
mutex_unlock(&dev_priv->sb_lock);
|
|
|
|
}
|
|
|
|
void chv_data_lane_soft_reset(struct intel_encoder *encoder,
|
|
const struct intel_crtc_state *crtc_state,
|
|
bool reset)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
|
|
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
|
|
enum pipe pipe = crtc->pipe;
|
|
uint32_t val;
|
|
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
|
|
if (reset)
|
|
val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
|
|
else
|
|
val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
|
|
|
|
if (crtc->config->lane_count > 2) {
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
|
|
if (reset)
|
|
val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
|
|
else
|
|
val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
|
|
}
|
|
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
|
|
val |= CHV_PCS_REQ_SOFTRESET_EN;
|
|
if (reset)
|
|
val &= ~DPIO_PCS_CLK_SOFT_RESET;
|
|
else
|
|
val |= DPIO_PCS_CLK_SOFT_RESET;
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
|
|
|
|
if (crtc->config->lane_count > 2) {
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
|
|
val |= CHV_PCS_REQ_SOFTRESET_EN;
|
|
if (reset)
|
|
val &= ~DPIO_PCS_CLK_SOFT_RESET;
|
|
else
|
|
val |= DPIO_PCS_CLK_SOFT_RESET;
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
|
|
}
|
|
}
|
|
|
|
void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
|
|
const struct intel_crtc_state *crtc_state)
|
|
{
|
|
struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
|
|
enum dpio_channel ch = vlv_dport_to_channel(dport);
|
|
enum pipe pipe = crtc->pipe;
|
|
unsigned int lane_mask =
|
|
intel_dp_unused_lane_mask(crtc_state->lane_count);
|
|
u32 val;
|
|
|
|
/*
|
|
* Must trick the second common lane into life.
|
|
* Otherwise we can't even access the PLL.
|
|
*/
|
|
if (ch == DPIO_CH0 && pipe == PIPE_B)
|
|
dport->release_cl2_override =
|
|
!chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
|
|
|
|
chv_phy_powergate_lanes(encoder, true, lane_mask);
|
|
|
|
mutex_lock(&dev_priv->sb_lock);
|
|
|
|
/* Assert data lane reset */
|
|
chv_data_lane_soft_reset(encoder, crtc_state, true);
|
|
|
|
/* program left/right clock distribution */
|
|
if (pipe != PIPE_B) {
|
|
val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
|
|
val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
|
|
if (ch == DPIO_CH0)
|
|
val |= CHV_BUFLEFTENA1_FORCE;
|
|
if (ch == DPIO_CH1)
|
|
val |= CHV_BUFRIGHTENA1_FORCE;
|
|
vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
|
|
} else {
|
|
val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
|
|
val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
|
|
if (ch == DPIO_CH0)
|
|
val |= CHV_BUFLEFTENA2_FORCE;
|
|
if (ch == DPIO_CH1)
|
|
val |= CHV_BUFRIGHTENA2_FORCE;
|
|
vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
|
|
}
|
|
|
|
/* program clock channel usage */
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
|
|
val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
|
|
if (pipe != PIPE_B)
|
|
val &= ~CHV_PCS_USEDCLKCHANNEL;
|
|
else
|
|
val |= CHV_PCS_USEDCLKCHANNEL;
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
|
|
|
|
if (crtc_state->lane_count > 2) {
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
|
|
val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
|
|
if (pipe != PIPE_B)
|
|
val &= ~CHV_PCS_USEDCLKCHANNEL;
|
|
else
|
|
val |= CHV_PCS_USEDCLKCHANNEL;
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
|
|
}
|
|
|
|
/*
|
|
* This a a bit weird since generally CL
|
|
* matches the pipe, but here we need to
|
|
* pick the CL based on the port.
|
|
*/
|
|
val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
|
|
if (pipe != PIPE_B)
|
|
val &= ~CHV_CMN_USEDCLKCHANNEL;
|
|
else
|
|
val |= CHV_CMN_USEDCLKCHANNEL;
|
|
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
|
|
|
|
mutex_unlock(&dev_priv->sb_lock);
|
|
}
|
|
|
|
void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
|
|
const struct intel_crtc_state *crtc_state)
|
|
{
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
|
struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
|
|
enum dpio_channel ch = vlv_dport_to_channel(dport);
|
|
enum pipe pipe = crtc->pipe;
|
|
int data, i, stagger;
|
|
u32 val;
|
|
|
|
mutex_lock(&dev_priv->sb_lock);
|
|
|
|
/* allow hardware to manage TX FIFO reset source */
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
|
|
val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
|
|
|
|
if (crtc_state->lane_count > 2) {
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
|
|
val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
|
|
}
|
|
|
|
/* Program Tx lane latency optimal setting*/
|
|
for (i = 0; i < crtc_state->lane_count; i++) {
|
|
/* Set the upar bit */
|
|
if (crtc_state->lane_count == 1)
|
|
data = 0x0;
|
|
else
|
|
data = (i == 1) ? 0x0 : 0x1;
|
|
vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
|
|
data << DPIO_UPAR_SHIFT);
|
|
}
|
|
|
|
/* Data lane stagger programming */
|
|
if (crtc_state->port_clock > 270000)
|
|
stagger = 0x18;
|
|
else if (crtc_state->port_clock > 135000)
|
|
stagger = 0xd;
|
|
else if (crtc_state->port_clock > 67500)
|
|
stagger = 0x7;
|
|
else if (crtc_state->port_clock > 33750)
|
|
stagger = 0x4;
|
|
else
|
|
stagger = 0x2;
|
|
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
|
|
val |= DPIO_TX2_STAGGER_MASK(0x1f);
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
|
|
|
|
if (crtc_state->lane_count > 2) {
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
|
|
val |= DPIO_TX2_STAGGER_MASK(0x1f);
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
|
|
}
|
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
|
|
DPIO_LANESTAGGER_STRAP(stagger) |
|
|
DPIO_LANESTAGGER_STRAP_OVRD |
|
|
DPIO_TX1_STAGGER_MASK(0x1f) |
|
|
DPIO_TX1_STAGGER_MULT(6) |
|
|
DPIO_TX2_STAGGER_MULT(0));
|
|
|
|
if (crtc_state->lane_count > 2) {
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
|
|
DPIO_LANESTAGGER_STRAP(stagger) |
|
|
DPIO_LANESTAGGER_STRAP_OVRD |
|
|
DPIO_TX1_STAGGER_MASK(0x1f) |
|
|
DPIO_TX1_STAGGER_MULT(7) |
|
|
DPIO_TX2_STAGGER_MULT(5));
|
|
}
|
|
|
|
/* Deassert data lane reset */
|
|
chv_data_lane_soft_reset(encoder, crtc_state, false);
|
|
|
|
mutex_unlock(&dev_priv->sb_lock);
|
|
}
|
|
|
|
void chv_phy_release_cl2_override(struct intel_encoder *encoder)
|
|
{
|
|
struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
if (dport->release_cl2_override) {
|
|
chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
|
|
dport->release_cl2_override = false;
|
|
}
|
|
}
|
|
|
|
void chv_phy_post_pll_disable(struct intel_encoder *encoder,
|
|
const struct intel_crtc_state *old_crtc_state)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
enum pipe pipe = to_intel_crtc(old_crtc_state->base.crtc)->pipe;
|
|
u32 val;
|
|
|
|
mutex_lock(&dev_priv->sb_lock);
|
|
|
|
/* disable left/right clock distribution */
|
|
if (pipe != PIPE_B) {
|
|
val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
|
|
val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
|
|
vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
|
|
} else {
|
|
val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
|
|
val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
|
|
vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
|
|
}
|
|
|
|
mutex_unlock(&dev_priv->sb_lock);
|
|
|
|
/*
|
|
* Leave the power down bit cleared for at least one
|
|
* lane so that chv_powergate_phy_ch() will power
|
|
* on something when the channel is otherwise unused.
|
|
* When the port is off and the override is removed
|
|
* the lanes power down anyway, so otherwise it doesn't
|
|
* really matter what the state of power down bits is
|
|
* after this.
|
|
*/
|
|
chv_phy_powergate_lanes(encoder, false, 0x0);
|
|
}
|
|
|
|
void vlv_set_phy_signal_level(struct intel_encoder *encoder,
|
|
u32 demph_reg_value, u32 preemph_reg_value,
|
|
u32 uniqtranscale_reg_value, u32 tx3_demph)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
|
|
struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
|
|
enum dpio_channel port = vlv_dport_to_channel(dport);
|
|
enum pipe pipe = intel_crtc->pipe;
|
|
|
|
mutex_lock(&dev_priv->sb_lock);
|
|
vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
|
|
vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
|
|
vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
|
|
uniqtranscale_reg_value);
|
|
vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
|
|
|
|
if (tx3_demph)
|
|
vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph);
|
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
|
|
vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
|
|
mutex_unlock(&dev_priv->sb_lock);
|
|
}
|
|
|
|
void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
|
|
const struct intel_crtc_state *crtc_state)
|
|
{
|
|
struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
|
|
enum dpio_channel port = vlv_dport_to_channel(dport);
|
|
enum pipe pipe = crtc->pipe;
|
|
|
|
/* Program Tx lane resets to default */
|
|
mutex_lock(&dev_priv->sb_lock);
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
|
|
DPIO_PCS_TX_LANE2_RESET |
|
|
DPIO_PCS_TX_LANE1_RESET);
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
|
|
DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
|
|
DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
|
|
(1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
|
|
DPIO_PCS_CLK_SOFT_RESET);
|
|
|
|
/* Fix up inter-pair skew failure */
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
|
|
vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
|
|
vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
|
|
mutex_unlock(&dev_priv->sb_lock);
|
|
}
|
|
|
|
void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
|
|
const struct intel_crtc_state *crtc_state)
|
|
{
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
|
struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
|
|
enum dpio_channel port = vlv_dport_to_channel(dport);
|
|
enum pipe pipe = crtc->pipe;
|
|
u32 val;
|
|
|
|
mutex_lock(&dev_priv->sb_lock);
|
|
|
|
/* Enable clock channels for this port */
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
|
|
val = 0;
|
|
if (pipe)
|
|
val |= (1<<21);
|
|
else
|
|
val &= ~(1<<21);
|
|
val |= 0x001000c4;
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
|
|
|
|
/* Program lane clock */
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
|
|
|
|
mutex_unlock(&dev_priv->sb_lock);
|
|
}
|
|
|
|
void vlv_phy_reset_lanes(struct intel_encoder *encoder,
|
|
const struct intel_crtc_state *old_crtc_state)
|
|
{
|
|
struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
|
|
enum dpio_channel port = vlv_dport_to_channel(dport);
|
|
enum pipe pipe = crtc->pipe;
|
|
|
|
mutex_lock(&dev_priv->sb_lock);
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
|
|
mutex_unlock(&dev_priv->sb_lock);
|
|
}
|