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![Ville Syrjälä](/assets/img/avatar_default.png)
i830 seems to occasionally forget the PIPESTAT enable bits when we read the register. These aren't the only registers on i830 that have problems with RMW, as reading the double buffered plane registers returns the latched value rather than the last written value. So something similar is perhaps going on with PIPESTAT. This corruption results on vblank interrupts occasionally turning off on their own, which leads to vblank timeouts and generally a stuck display subsystem. So let's not RMW the pipestat enable bits, and instead use the cached copy we have around. Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170914151731.5034-1-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
456 lines
14 KiB
C
456 lines
14 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Daniel Vetter <daniel.vetter@ffwll.ch>
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*
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*/
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#include "i915_drv.h"
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#include "intel_drv.h"
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/**
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* DOC: fifo underrun handling
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*
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* The i915 driver checks for display fifo underruns using the interrupt signals
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* provided by the hardware. This is enabled by default and fairly useful to
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* debug display issues, especially watermark settings.
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*
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* If an underrun is detected this is logged into dmesg. To avoid flooding logs
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* and occupying the cpu underrun interrupts are disabled after the first
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* occurrence until the next modeset on a given pipe.
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*
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* Note that underrun detection on gmch platforms is a bit more ugly since there
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* is no interrupt (despite that the signalling bit is in the PIPESTAT pipe
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* interrupt register). Also on some other platforms underrun interrupts are
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* shared, which means that if we detect an underrun we need to disable underrun
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* reporting on all pipes.
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*
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* The code also supports underrun detection on the PCH transcoder.
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*/
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static bool ivb_can_enable_err_int(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *crtc;
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enum pipe pipe;
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lockdep_assert_held(&dev_priv->irq_lock);
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for_each_pipe(dev_priv, pipe) {
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crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
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if (crtc->cpu_fifo_underrun_disabled)
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return false;
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}
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return true;
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}
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static bool cpt_can_enable_serr_int(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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enum pipe pipe;
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struct intel_crtc *crtc;
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lockdep_assert_held(&dev_priv->irq_lock);
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for_each_pipe(dev_priv, pipe) {
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crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
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if (crtc->pch_fifo_underrun_disabled)
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return false;
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}
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return true;
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}
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static void i9xx_check_fifo_underruns(struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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i915_reg_t reg = PIPESTAT(crtc->pipe);
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u32 enable_mask;
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lockdep_assert_held(&dev_priv->irq_lock);
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if ((I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)
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return;
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enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe);
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I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
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POSTING_READ(reg);
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trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe);
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DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe));
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}
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static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
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enum pipe pipe,
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bool enable, bool old)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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i915_reg_t reg = PIPESTAT(pipe);
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lockdep_assert_held(&dev_priv->irq_lock);
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if (enable) {
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u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
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I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
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POSTING_READ(reg);
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} else {
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if (old && I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS)
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DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
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}
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}
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static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
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enum pipe pipe, bool enable)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
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DE_PIPEB_FIFO_UNDERRUN;
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if (enable)
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ilk_enable_display_irq(dev_priv, bit);
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else
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ilk_disable_display_irq(dev_priv, bit);
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}
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static void ivybridge_check_fifo_underruns(struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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enum pipe pipe = crtc->pipe;
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uint32_t err_int = I915_READ(GEN7_ERR_INT);
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lockdep_assert_held(&dev_priv->irq_lock);
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if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0)
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return;
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I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
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POSTING_READ(GEN7_ERR_INT);
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trace_intel_cpu_fifo_underrun(dev_priv, pipe);
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DRM_ERROR("fifo underrun on pipe %c\n", pipe_name(pipe));
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}
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static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
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enum pipe pipe,
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bool enable, bool old)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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if (enable) {
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I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
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if (!ivb_can_enable_err_int(dev))
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return;
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ilk_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
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} else {
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ilk_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
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if (old &&
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I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
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DRM_ERROR("uncleared fifo underrun on pipe %c\n",
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pipe_name(pipe));
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}
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}
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}
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static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
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enum pipe pipe, bool enable)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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if (enable)
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bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);
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else
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bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);
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}
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static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
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enum pipe pch_transcoder,
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bool enable)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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uint32_t bit = (pch_transcoder == PIPE_A) ?
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SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
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if (enable)
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ibx_enable_display_interrupt(dev_priv, bit);
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else
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ibx_disable_display_interrupt(dev_priv, bit);
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}
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static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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enum pipe pch_transcoder = crtc->pipe;
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uint32_t serr_int = I915_READ(SERR_INT);
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lockdep_assert_held(&dev_priv->irq_lock);
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if ((serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) == 0)
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return;
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I915_WRITE(SERR_INT, SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
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POSTING_READ(SERR_INT);
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trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder);
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DRM_ERROR("pch fifo underrun on pch transcoder %c\n",
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pipe_name(pch_transcoder));
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}
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static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
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enum pipe pch_transcoder,
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bool enable, bool old)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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if (enable) {
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I915_WRITE(SERR_INT,
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SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
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if (!cpt_can_enable_serr_int(dev))
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return;
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ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
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} else {
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ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
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if (old && I915_READ(SERR_INT) &
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SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) {
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DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n",
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pipe_name(pch_transcoder));
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}
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}
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}
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static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
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enum pipe pipe, bool enable)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
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bool old;
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lockdep_assert_held(&dev_priv->irq_lock);
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old = !crtc->cpu_fifo_underrun_disabled;
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crtc->cpu_fifo_underrun_disabled = !enable;
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if (HAS_GMCH_DISPLAY(dev_priv))
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i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
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else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
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ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
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else if (IS_GEN7(dev_priv))
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ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
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else if (INTEL_GEN(dev_priv) >= 8)
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broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
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return old;
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}
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/**
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* intel_set_cpu_fifo_underrun_reporting - set cpu fifo underrrun reporting state
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* @dev_priv: i915 device instance
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* @pipe: (CPU) pipe to set state for
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* @enable: whether underruns should be reported or not
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*
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* This function sets the fifo underrun state for @pipe. It is used in the
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* modeset code to avoid false positives since on many platforms underruns are
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* expected when disabling or enabling the pipe.
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*
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* Notice that on some platforms disabling underrun reports for one pipe
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* disables for all due to shared interrupts. Actual reporting is still per-pipe
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* though.
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*
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* Returns the previous state of underrun reporting.
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*/
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bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
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enum pipe pipe, bool enable)
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{
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unsigned long flags;
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bool ret;
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spin_lock_irqsave(&dev_priv->irq_lock, flags);
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ret = __intel_set_cpu_fifo_underrun_reporting(&dev_priv->drm, pipe,
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enable);
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spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
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return ret;
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}
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/**
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* intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting state
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* @dev_priv: i915 device instance
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* @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
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* @enable: whether underruns should be reported or not
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*
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* This function makes us disable or enable PCH fifo underruns for a specific
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* PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
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* underrun reporting for one transcoder may also disable all the other PCH
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* error interruts for the other transcoders, due to the fact that there's just
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* one interrupt mask/enable bit for all the transcoders.
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*
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* Returns the previous state of underrun reporting.
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*/
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bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
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enum pipe pch_transcoder,
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bool enable)
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{
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struct intel_crtc *crtc =
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intel_get_crtc_for_pipe(dev_priv, pch_transcoder);
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unsigned long flags;
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bool old;
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/*
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* NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
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* has only one pch transcoder A that all pipes can use. To avoid racy
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* pch transcoder -> pipe lookups from interrupt code simply store the
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* underrun statistics in crtc A. Since we never expose this anywhere
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* nor use it outside of the fifo underrun code here using the "wrong"
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* crtc on LPT won't cause issues.
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*/
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spin_lock_irqsave(&dev_priv->irq_lock, flags);
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old = !crtc->pch_fifo_underrun_disabled;
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crtc->pch_fifo_underrun_disabled = !enable;
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if (HAS_PCH_IBX(dev_priv))
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ibx_set_fifo_underrun_reporting(&dev_priv->drm,
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pch_transcoder,
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enable);
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else
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cpt_set_fifo_underrun_reporting(&dev_priv->drm,
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pch_transcoder,
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enable, old);
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spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
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return old;
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}
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/**
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* intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt
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* @dev_priv: i915 device instance
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* @pipe: (CPU) pipe to set state for
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*
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* This handles a CPU fifo underrun interrupt, generating an underrun warning
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* into dmesg if underrun reporting is enabled and then disables the underrun
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* interrupt to avoid an irq storm.
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*/
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void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
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enum pipe pipe)
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{
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struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
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/* We may be called too early in init, thanks BIOS! */
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if (crtc == NULL)
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return;
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/* GMCH can't disable fifo underruns, filter them. */
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if (HAS_GMCH_DISPLAY(dev_priv) &&
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crtc->cpu_fifo_underrun_disabled)
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return;
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if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) {
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trace_intel_cpu_fifo_underrun(dev_priv, pipe);
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DRM_ERROR("CPU pipe %c FIFO underrun\n",
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pipe_name(pipe));
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}
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intel_fbc_handle_fifo_underrun_irq(dev_priv);
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}
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/**
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* intel_pch_fifo_underrun_irq_handler - handle PCH fifo underrun interrupt
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* @dev_priv: i915 device instance
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* @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
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*
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* This handles a PCH fifo underrun interrupt, generating an underrun warning
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* into dmesg if underrun reporting is enabled and then disables the underrun
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* interrupt to avoid an irq storm.
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*/
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void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
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enum pipe pch_transcoder)
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{
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if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder,
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false)) {
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trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder);
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DRM_ERROR("PCH transcoder %c FIFO underrun\n",
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pipe_name(pch_transcoder));
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}
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}
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/**
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* intel_check_cpu_fifo_underruns - check for CPU fifo underruns immediately
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* @dev_priv: i915 device instance
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*
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* Check for CPU fifo underruns immediately. Useful on IVB/HSW where the shared
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* error interrupt may have been disabled, and so CPU fifo underruns won't
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* necessarily raise an interrupt, and on GMCH platforms where underruns never
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* raise an interrupt.
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*/
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void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv)
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{
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struct intel_crtc *crtc;
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spin_lock_irq(&dev_priv->irq_lock);
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for_each_intel_crtc(&dev_priv->drm, crtc) {
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if (crtc->cpu_fifo_underrun_disabled)
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continue;
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if (HAS_GMCH_DISPLAY(dev_priv))
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i9xx_check_fifo_underruns(crtc);
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else if (IS_GEN7(dev_priv))
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ivybridge_check_fifo_underruns(crtc);
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}
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spin_unlock_irq(&dev_priv->irq_lock);
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}
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/**
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* intel_check_pch_fifo_underruns - check for PCH fifo underruns immediately
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* @dev_priv: i915 device instance
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*
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* Check for PCH fifo underruns immediately. Useful on CPT/PPT where the shared
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* error interrupt may have been disabled, and so PCH fifo underruns won't
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* necessarily raise an interrupt.
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*/
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void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv)
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{
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struct intel_crtc *crtc;
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spin_lock_irq(&dev_priv->irq_lock);
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for_each_intel_crtc(&dev_priv->drm, crtc) {
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if (crtc->pch_fifo_underrun_disabled)
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continue;
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if (HAS_PCH_CPT(dev_priv))
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cpt_check_pch_fifo_underruns(crtc);
|
|
}
|
|
|
|
spin_unlock_irq(&dev_priv->irq_lock);
|
|
}
|