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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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9e71296303
When starting an SMP hardware thread, copy the cache partition configuration so that the threads share the same cache partitions. Also enable the GCOn bit if running in the local half of the virtual address space to enable coherency of shared local cache partitions. An atomic unlock system event is executed by the new cpu before any memory is read to ensure that any writes made by the boot cpu prior to full coherency taking effect are visible to the new cpu. This is to allow SMP to work even when the bootloader hasn't configured the caches for coherency. A log message is printed to describe the cache partition changes so that the user is aware of potential unintentional cache wastage if they've configured the cache partitions in the wrong way. Signed-off-by: James Hogan <james.hogan@imgtec.com>
65 lines
1.7 KiB
ArmAsm
65 lines
1.7 KiB
ArmAsm
! Copyright 2005,2006,2007,2009 Imagination Technologies
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#include <linux/init.h>
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#include <asm/metag_mem.h>
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#include <generated/asm-offsets.h>
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#undef __exit
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__HEAD
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! Setup the stack and get going into _metag_start_kernel
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.global __start
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.type __start,function
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__start:
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! D1Ar1 contains pTBI (ISTAT)
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! D0Ar2 contains pTBI
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! D1Ar3 contains __pTBISegs
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! D0Ar4 contains kernel arglist pointer
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MOVT D0Re0,#HI(___pTBIs)
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ADD D0Re0,D0Re0,#LO(___pTBIs)
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SETL [D0Re0],D0Ar2,D1Ar1
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MOVT D0Re0,#HI(___pTBISegs)
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ADD D0Re0,D0Re0,#LO(___pTBISegs)
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SETD [D0Re0],D1Ar3
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MOV A0FrP,#0
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MOV D0Re0,#0
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MOV D1Re0,#0
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MOV D1Ar3,#0
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MOV D1Ar1,D0Ar4 !Store kernel boot params
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MOV D1Ar5,#0
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MOV D0Ar6,#0
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#ifdef CONFIG_METAG_DSP
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MOV D0.8,#0
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#endif
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MOVT A0StP,#HI(_init_thread_union)
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ADD A0StP,A0StP,#LO(_init_thread_union)
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ADD A0StP,A0StP,#THREAD_INFO_SIZE
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MOVT D1RtP,#HI(_metag_start_kernel)
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CALL D1RtP,#LO(_metag_start_kernel)
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.size __start,.-__start
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!! Needed by TBX
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.global __exit
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.type __exit,function
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__exit:
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XOR TXENABLE,D0Re0,D0Re0
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.size __exit,.-__exit
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#ifdef CONFIG_SMP
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.global _secondary_startup
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.type _secondary_startup,function
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_secondary_startup:
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#if CONFIG_PAGE_OFFSET < LINGLOBAL_BASE
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! In case GCOn has just been turned on we need to fence any writes that
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! the boot thread might have performed prior to coherency taking effect.
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MOVT D0Re0,#HI(LINSYSEVENT_WR_ATOMIC_UNLOCK)
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MOV D1Re0,#0
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SETD [D0Re0], D1Re0
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#endif
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MOVT A0StP,#HI(_secondary_data_stack)
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ADD A0StP,A0StP,#LO(_secondary_data_stack)
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GETD A0StP,[A0StP]
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ADD A0StP,A0StP,#THREAD_INFO_SIZE
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B _secondary_start_kernel
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.size _secondary_startup,.-_secondary_startup
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#endif
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