Damien Le Moal 956d705dd2 riscv: Unaligned load/store handling for M_MODE ... Add handlers for unaligned load and store traps that may be generated by applications. Code heavily inspired from the OpenSBI project. Handling of the unaligned access traps is suitable for applications compiled with or without compressed instructions and is independent of the kernel CONFIG_RISCV_ISA_C option value. Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2020-04-03 10:45:33 -07:00
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boot	riscv: Fix gitignore	2020-02-19 16:13:51 -08:00
configs	riscv: Delete CONFIG_SYSFS_SYSCALL from defconfigs	2020-03-03 10:28:11 -08:00
include	RISC-V: Support cpu hotplug	2020-03-31 11:28:30 -07:00
kernel	riscv: Unaligned load/store handling for M_MODE	2020-04-03 10:45:33 -07:00
lib	RISC-V: Stop using LOCAL for the uaccess fixups	2020-03-03 10:45:14 -08:00
mm	riscv: Add support to dump the kernel page tables	2020-03-26 09:29:49 -07:00
net	Merge git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-next	2019-12-27 14:20:10 -08:00
Kbuild	riscv: add arch/riscv/Kbuild	2019-08-30 17:34:00 -07:00
Kconfig	RISC-V: Support cpu hotplug	2020-03-31 11:28:30 -07:00
Kconfig.debug	RISC-V: Remove EARLY_PRINTK support	2018-12-17 10:23:46 -08:00
Kconfig.socs	riscv: only select serial sifive if TTY is enabled	2019-12-08 20:29:01 -08:00
Makefile	riscv: provide a flat image loader	2019-11-17 15:17:39 -08:00