mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-31 08:28:13 +00:00
42dec9a936
- Improve Intel uncore PMU support:
- Parse uncore 'discovery tables' - a new hardware capability enumeration method
introduced on the latest Intel platforms. This table is in a well-defined PCI
namespace location and is read via MMIO. It is organized in an rbtree.
These uncore tables will allow the discovery of standard counter blocks, but
fancier counters still need to be enumerated explicitly.
- Add Alder Lake support
- Improve IIO stacks to PMON mapping support on Skylake servers
- Add Intel Alder Lake PMU support - which requires the introduction of 'hybrid' CPUs
and PMUs. Alder Lake is a mix of Golden Cove ('big') and Gracemont ('small' - Atom derived)
cores.
The CPU-side feature set is entirely symmetrical - but on the PMU side there's
core type dependent PMU functionality.
- Reduce data loss with CPU level hardware tracing on Intel PT / AUX profiling, by
fixing the AUX allocation watermark logic.
- Improve ring buffer allocation on NUMA systems
- Put 'struct perf_event' into their separate kmem_cache pool
- Add support for synchronous signals for select perf events. The immediate motivation
is to support low-overhead sampling-based race detection for user-space code. The
feature consists of the following main changes:
- Add thread-only event inheritance via perf_event_attr::inherit_thread, which limits
inheritance of events to CLONE_THREAD.
- Add the ability for events to not leak through exec(), via perf_event_attr::remove_on_exec.
- Allow the generation of SIGTRAP via perf_event_attr::sigtrap, extend siginfo with an u64
::si_perf, and add the breakpoint information to ::si_addr and ::si_perf if the event is
PERF_TYPE_BREAKPOINT.
The siginfo support is adequate for breakpoints right now - but the new field can be used
to introduce support for other types of metadata passed over siginfo as well.
- Misc fixes, cleanups and smaller updates.
Signed-off-by: Ingo Molnar <mingo@kernel.org>
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Merge tag 'perf-core-2021-04-28' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull perf event updates from Ingo Molnar:
- Improve Intel uncore PMU support:
- Parse uncore 'discovery tables' - a new hardware capability
enumeration method introduced on the latest Intel platforms. This
table is in a well-defined PCI namespace location and is read via
MMIO. It is organized in an rbtree.
These uncore tables will allow the discovery of standard counter
blocks, but fancier counters still need to be enumerated
explicitly.
- Add Alder Lake support
- Improve IIO stacks to PMON mapping support on Skylake servers
- Add Intel Alder Lake PMU support - which requires the introduction of
'hybrid' CPUs and PMUs. Alder Lake is a mix of Golden Cove ('big')
and Gracemont ('small' - Atom derived) cores.
The CPU-side feature set is entirely symmetrical - but on the PMU
side there's core type dependent PMU functionality.
- Reduce data loss with CPU level hardware tracing on Intel PT / AUX
profiling, by fixing the AUX allocation watermark logic.
- Improve ring buffer allocation on NUMA systems
- Put 'struct perf_event' into their separate kmem_cache pool
- Add support for synchronous signals for select perf events. The
immediate motivation is to support low-overhead sampling-based race
detection for user-space code. The feature consists of the following
main changes:
- Add thread-only event inheritance via
perf_event_attr::inherit_thread, which limits inheritance of
events to CLONE_THREAD.
- Add the ability for events to not leak through exec(), via
perf_event_attr::remove_on_exec.
- Allow the generation of SIGTRAP via perf_event_attr::sigtrap,
extend siginfo with an u64 ::si_perf, and add the breakpoint
information to ::si_addr and ::si_perf if the event is
PERF_TYPE_BREAKPOINT.
The siginfo support is adequate for breakpoints right now - but the
new field can be used to introduce support for other types of
metadata passed over siginfo as well.
- Misc fixes, cleanups and smaller updates.
* tag 'perf-core-2021-04-28' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (53 commits)
signal, perf: Add missing TRAP_PERF case in siginfo_layout()
signal, perf: Fix siginfo_t by avoiding u64 on 32-bit architectures
perf/x86: Allow for 8<num_fixed_counters<16
perf/x86/rapl: Add support for Intel Alder Lake
perf/x86/cstate: Add Alder Lake CPU support
perf/x86/msr: Add Alder Lake CPU support
perf/x86/intel/uncore: Add Alder Lake support
perf: Extend PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE
perf/x86/intel: Add Alder Lake Hybrid support
perf/x86: Support filter_match callback
perf/x86/intel: Add attr_update for Hybrid PMUs
perf/x86: Add structures for the attributes of Hybrid PMUs
perf/x86: Register hybrid PMUs
perf/x86: Factor out x86_pmu_show_pmu_cap
perf/x86: Remove temporary pmu assignment in event_init
perf/x86/intel: Factor out intel_pmu_check_extra_regs
perf/x86/intel: Factor out intel_pmu_check_event_constraints
perf/x86/intel: Factor out intel_pmu_check_num_counters
perf/x86: Hybrid PMU support for extra_regs
perf/x86: Hybrid PMU support for event constraints
...
75 lines
1.9 KiB
C
75 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_CPU_H
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#define _ASM_X86_CPU_H
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#include <linux/device.h>
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#include <linux/cpu.h>
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#include <linux/topology.h>
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#include <linux/nodemask.h>
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#include <linux/percpu.h>
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#ifdef CONFIG_SMP
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extern void prefill_possible_map(void);
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#else /* CONFIG_SMP */
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static inline void prefill_possible_map(void) {}
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#define cpu_physical_id(cpu) boot_cpu_physical_apicid
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#define cpu_acpi_id(cpu) 0
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#define safe_smp_processor_id() 0
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#endif /* CONFIG_SMP */
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struct x86_cpu {
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struct cpu cpu;
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};
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#ifdef CONFIG_HOTPLUG_CPU
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extern int arch_register_cpu(int num);
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extern void arch_unregister_cpu(int);
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extern void start_cpu0(void);
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#ifdef CONFIG_DEBUG_HOTPLUG_CPU0
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extern int _debug_hotplug_cpu(int cpu, int action);
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#endif
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#endif
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int mwait_usable(const struct cpuinfo_x86 *);
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unsigned int x86_family(unsigned int sig);
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unsigned int x86_model(unsigned int sig);
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unsigned int x86_stepping(unsigned int sig);
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#ifdef CONFIG_CPU_SUP_INTEL
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extern void __init sld_setup(struct cpuinfo_x86 *c);
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extern void switch_to_sld(unsigned long tifn);
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extern bool handle_user_split_lock(struct pt_regs *regs, long error_code);
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extern bool handle_guest_split_lock(unsigned long ip);
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extern void handle_bus_lock(struct pt_regs *regs);
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u8 get_this_hybrid_cpu_type(void);
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#else
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static inline void __init sld_setup(struct cpuinfo_x86 *c) {}
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static inline void switch_to_sld(unsigned long tifn) {}
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static inline bool handle_user_split_lock(struct pt_regs *regs, long error_code)
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{
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return false;
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}
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static inline bool handle_guest_split_lock(unsigned long ip)
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{
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return false;
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}
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static inline void handle_bus_lock(struct pt_regs *regs) {}
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static inline u8 get_this_hybrid_cpu_type(void)
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{
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return 0;
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}
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#endif
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#ifdef CONFIG_IA32_FEAT_CTL
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void init_ia32_feat_ctl(struct cpuinfo_x86 *c);
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#else
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static inline void init_ia32_feat_ctl(struct cpuinfo_x86 *c) {}
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#endif
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#endif /* _ASM_X86_CPU_H */
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