Chen-Yu Tsai 95e94c1fad clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output ... Some clock modules on the A31 use PLL6x2 as one of their inputs. This patch changes the PLL6 implementation for A31 to a divs clock, i.e. clock with multiple outputs that have different dividers. The first output will be the normal PLL6 output, and the second will be PLL6x2. This patch fixes the PLL6 N factor in the clock driver, and removes any /2 dividers in the PLL6 factors clock part. The N factor counts from 1 to 32, mapping to values 0 to 31, as shown in the A31 manual. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>		2014-11-23 17:02:56 +01:00
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clk-a10-hosc.c	clk: sunxi: Move the 24M oscillator to a file of its own	2014-06-11 09:58:44 +02:00
clk-a20-gmac.c	clk: sunxi: add __iomem markings to MMIO pointers	2014-07-28 15:39:05 -07:00
clk-factors.c	clk: sunxi: make factors clock mux mask configurable	2014-10-21 21:40:56 +02:00
clk-factors.h	clk: sunxi: make factors clock mux mask configurable	2014-10-21 21:40:56 +02:00
clk-mod0.c	clk: sunxi: make factors clock mux mask configurable	2014-10-21 21:40:56 +02:00
clk-sun6i-apb0-gates.c	clk: Remove .owner field for driver	2014-09-25 17:43:31 -07:00
clk-sun6i-apb0.c	clk: Remove .owner field for driver	2014-09-25 17:43:31 -07:00
clk-sun6i-ar100.c	clk: Remove .owner field for driver	2014-09-25 17:43:31 -07:00
clk-sun8i-apb0.c	clk: Remove .owner field for driver	2014-09-25 17:43:31 -07:00
clk-sun8i-mbus.c	clk: sunxi: make factors clock mux mask configurable	2014-10-21 21:40:56 +02:00
clk-sun9i-core.c	clk: sunxi: Add support for A80 basic bus clocks	2014-10-21 21:45:48 +02:00
clk-sunxi.c	clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output	2014-11-23 17:02:56 +01:00
Makefile	clk: sunxi: Add support for A80 basic bus clocks	2014-10-21 21:45:48 +02:00