Clément Léger 1f1c2a3452 riscv: fix misaligned access handling of C.SWSP and C.SDSP ... [ Upstream commit 22e0eb0483 ] This is a backport of a fix that was done in OpenSBI: ec0559eb315b ("lib: sbi_misaligned_ldst: Fix handling of C.SWSP and C.SDSP"). Unlike C.LWSP/C.LDSP, these encodings can be used with the zero register, so checking that the rs2 field is non-zero is unnecessary. Additionally, the previous check was incorrect since it was checking the immediate field of the instruction instead of the rs2 field. Fixes: 956d705dd2 ("riscv: Unaligned load/store handling for M_MODE") Signed-off-by: Clément Léger <cleger@rivosinc.com> Link: https://lore.kernel.org/r/20231103090223.702340-1-cleger@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Sasha Levin <sashal@kernel.org>		2023-12-13 18:27:02 +01:00
..
boot	riscv: dts: sifive unleashed: Add PWM controlled LEDs	2022-12-02 17:39:57 +01:00
configs	riscv: defconfig: enable gpio support for HiFive Unleashed	2021-01-27 11:55:01 +01:00
include	riscv,mmio: Fix readX()-to-delay() ordering	2023-08-16 18:20:59 +02:00
kernel	riscv: fix misaligned access handling of C.SWSP and C.SDSP	2023-12-13 18:27:02 +01:00
lib
mm	riscv: Fixup race condition on PG_dcache_clean in flush_icache_pte	2023-02-15 17:22:26 +01:00
net	riscv, bpf: Sign-extend return values	2023-10-25 11:54:13 +02:00
Kbuild
Kconfig	riscv: fix kprobe __user string arg print fault issue	2023-06-14 11:09:57 +02:00
Kconfig.debug
Kconfig.socs
Makefile	riscv: Handle zicsr/zifencei issues between clang and binutils	2023-04-20 12:10:28 +02:00