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4ff4c745a1
Introduce an architecture function that architectures can use to set
up ("prepare") SYNC_CORE commands.
The function will be used by RISC-V to update its "deferred icache-
flush" data structures (icache_stale_mask).
Architectures defining prepare_sync_core_cmd() static inline need to
select ARCH_HAS_PREPARE_SYNC_CORE_CMD.
Suggested-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Signed-off-by: Andrea Parri <parri.andrea@gmail.com>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Link: https://lore.kernel.org/r/20240131144936.29190-4-parri.andrea@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
35 lines
1 KiB
C
35 lines
1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _LINUX_SYNC_CORE_H
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#define _LINUX_SYNC_CORE_H
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#ifdef CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE
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#include <asm/sync_core.h>
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#else
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/*
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* This is a dummy sync_core_before_usermode() implementation that can be used
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* on all architectures which return to user-space through core serializing
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* instructions.
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* If your architecture returns to user-space through non-core-serializing
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* instructions, you need to write your own functions.
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*/
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static inline void sync_core_before_usermode(void)
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{
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}
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#endif
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#ifdef CONFIG_ARCH_HAS_PREPARE_SYNC_CORE_CMD
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#include <asm/sync_core.h>
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#else
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/*
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* This is a dummy prepare_sync_core_cmd() implementation that can be used on
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* all architectures which provide unconditional core serializing instructions
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* in switch_mm().
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* If your architecture doesn't provide such core serializing instructions in
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* switch_mm(), you may need to write your own functions.
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*/
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static inline void prepare_sync_core_cmd(struct mm_struct *mm)
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{
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}
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#endif
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#endif /* _LINUX_SYNC_CORE_H */
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