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![Christoph Hellwig](/assets/img/avatar_default.png)
ioremap has provided non-cached semantics by default since the Linux 2.6 days, so remove the additional ioremap_nocache interface. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Arnd Bergmann <arnd@arndb.de>
228 lines
5.7 KiB
C
228 lines
5.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* drivers/soc/tegra/flowctrl.c
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*
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* Functions and macros to control the flowcontroller
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*
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* Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
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*/
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#include <linux/cpumask.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <soc/tegra/common.h>
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#include <soc/tegra/flowctrl.h>
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#include <soc/tegra/fuse.h>
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static u8 flowctrl_offset_halt_cpu[] = {
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FLOW_CTRL_HALT_CPU0_EVENTS,
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FLOW_CTRL_HALT_CPU1_EVENTS,
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FLOW_CTRL_HALT_CPU1_EVENTS + 8,
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FLOW_CTRL_HALT_CPU1_EVENTS + 16,
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};
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static u8 flowctrl_offset_cpu_csr[] = {
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FLOW_CTRL_CPU0_CSR,
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FLOW_CTRL_CPU1_CSR,
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FLOW_CTRL_CPU1_CSR + 8,
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FLOW_CTRL_CPU1_CSR + 16,
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};
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static void __iomem *tegra_flowctrl_base;
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static void flowctrl_update(u8 offset, u32 value)
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{
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if (WARN_ONCE(IS_ERR_OR_NULL(tegra_flowctrl_base),
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"Tegra flowctrl not initialised!\n"))
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return;
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writel(value, tegra_flowctrl_base + offset);
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/* ensure the update has reached the flow controller */
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wmb();
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readl_relaxed(tegra_flowctrl_base + offset);
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}
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u32 flowctrl_read_cpu_csr(unsigned int cpuid)
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{
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u8 offset = flowctrl_offset_cpu_csr[cpuid];
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if (WARN_ONCE(IS_ERR_OR_NULL(tegra_flowctrl_base),
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"Tegra flowctrl not initialised!\n"))
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return 0;
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return readl(tegra_flowctrl_base + offset);
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}
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void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
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{
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return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value);
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}
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void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value)
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{
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return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value);
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}
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void flowctrl_cpu_suspend_enter(unsigned int cpuid)
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{
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unsigned int reg;
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int i;
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reg = flowctrl_read_cpu_csr(cpuid);
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switch (tegra_get_chip_id()) {
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case TEGRA20:
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/* clear wfe bitmap */
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reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
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/* clear wfi bitmap */
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reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
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/* pwr gating on wfe */
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reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid;
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break;
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case TEGRA30:
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case TEGRA114:
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case TEGRA124:
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/* clear wfe bitmap */
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reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
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/* clear wfi bitmap */
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reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
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if (tegra_get_chip_id() == TEGRA30) {
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/*
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* The wfi doesn't work well on Tegra30 because
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* CPU hangs under some odd circumstances after
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* power-gating (like memory running off PLLP),
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* hence use wfe that is working perfectly fine.
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* Note that Tegra30 TRM doc clearly stands that
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* wfi should be used for the "Cluster Switching",
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* while wfe for the power-gating, just like it
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* is done on Tegra20.
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*/
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reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid;
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} else {
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/* pwr gating on wfi */
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reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid;
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}
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break;
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}
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reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */
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reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */
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reg |= FLOW_CTRL_CSR_ENABLE; /* pwr gating */
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flowctrl_write_cpu_csr(cpuid, reg);
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for (i = 0; i < num_possible_cpus(); i++) {
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if (i == cpuid)
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continue;
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reg = flowctrl_read_cpu_csr(i);
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reg |= FLOW_CTRL_CSR_EVENT_FLAG;
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reg |= FLOW_CTRL_CSR_INTR_FLAG;
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flowctrl_write_cpu_csr(i, reg);
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}
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}
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void flowctrl_cpu_suspend_exit(unsigned int cpuid)
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{
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unsigned int reg;
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/* Disable powergating via flow controller for CPU0 */
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reg = flowctrl_read_cpu_csr(cpuid);
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switch (tegra_get_chip_id()) {
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case TEGRA20:
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/* clear wfe bitmap */
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reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
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/* clear wfi bitmap */
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reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
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break;
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case TEGRA30:
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case TEGRA114:
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case TEGRA124:
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/* clear wfe bitmap */
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reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
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/* clear wfi bitmap */
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reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
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break;
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}
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reg &= ~FLOW_CTRL_CSR_ENABLE; /* clear enable */
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reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr */
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reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */
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flowctrl_write_cpu_csr(cpuid, reg);
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}
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static int tegra_flowctrl_probe(struct platform_device *pdev)
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{
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void __iomem *base = tegra_flowctrl_base;
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struct resource *res;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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tegra_flowctrl_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(tegra_flowctrl_base))
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return PTR_ERR(tegra_flowctrl_base);
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iounmap(base);
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return 0;
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}
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static const struct of_device_id tegra_flowctrl_match[] = {
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{ .compatible = "nvidia,tegra210-flowctrl" },
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{ .compatible = "nvidia,tegra124-flowctrl" },
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{ .compatible = "nvidia,tegra114-flowctrl" },
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{ .compatible = "nvidia,tegra30-flowctrl" },
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{ .compatible = "nvidia,tegra20-flowctrl" },
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{ }
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};
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static struct platform_driver tegra_flowctrl_driver = {
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.driver = {
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.name = "tegra-flowctrl",
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.suppress_bind_attrs = true,
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.of_match_table = tegra_flowctrl_match,
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},
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.probe = tegra_flowctrl_probe,
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};
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builtin_platform_driver(tegra_flowctrl_driver);
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static int __init tegra_flowctrl_init(void)
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{
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struct resource res;
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struct device_node *np;
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if (!soc_is_tegra())
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return 0;
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np = of_find_matching_node(NULL, tegra_flowctrl_match);
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if (np) {
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if (of_address_to_resource(np, 0, &res) < 0) {
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pr_err("failed to get flowctrl register\n");
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return -ENXIO;
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}
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of_node_put(np);
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} else if (IS_ENABLED(CONFIG_ARM)) {
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/*
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* Hardcoded fallback for 32-bit Tegra
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* devices if device tree node is missing.
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*/
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res.start = 0x60007000;
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res.end = 0x60007fff;
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res.flags = IORESOURCE_MEM;
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} else {
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/*
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* At this point we're running on a Tegra,
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* that doesn't support the flow controller
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* (eg. Tegra186), so just return.
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*/
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return 0;
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}
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tegra_flowctrl_base = ioremap(res.start, resource_size(&res));
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if (!tegra_flowctrl_base)
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return -ENXIO;
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return 0;
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}
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early_initcall(tegra_flowctrl_init);
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