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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 and only version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 294 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.825281744@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
192 lines
6.1 KiB
C
192 lines
6.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
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* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*/
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#ifndef __QCA8K_H
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#define __QCA8K_H
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#include <linux/delay.h>
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#include <linux/regmap.h>
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#define QCA8K_NUM_PORTS 7
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#define PHY_ID_QCA8337 0x004dd036
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#define QCA8K_ID_QCA8337 0x13
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#define QCA8K_NUM_FDB_RECORDS 2048
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#define QCA8K_CPU_PORT 0
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/* Global control registers */
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#define QCA8K_REG_MASK_CTRL 0x000
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#define QCA8K_MASK_CTRL_ID_M 0xff
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#define QCA8K_MASK_CTRL_ID_S 8
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#define QCA8K_REG_PORT0_PAD_CTRL 0x004
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#define QCA8K_REG_PORT5_PAD_CTRL 0x008
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#define QCA8K_REG_PORT6_PAD_CTRL 0x00c
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#define QCA8K_PORT_PAD_RGMII_EN BIT(26)
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#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) \
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((0x8 + (x & 0x3)) << 22)
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#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) \
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((0x10 + (x & 0x3)) << 20)
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#define QCA8K_MAX_DELAY 3
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#define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24)
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#define QCA8K_PORT_PAD_SGMII_EN BIT(7)
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#define QCA8K_REG_MODULE_EN 0x030
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#define QCA8K_MODULE_EN_MIB BIT(0)
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#define QCA8K_REG_MIB 0x034
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#define QCA8K_MIB_FLUSH BIT(24)
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#define QCA8K_MIB_CPU_KEEP BIT(20)
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#define QCA8K_MIB_BUSY BIT(17)
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#define QCA8K_MDIO_MASTER_CTRL 0x3c
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#define QCA8K_MDIO_MASTER_BUSY BIT(31)
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#define QCA8K_MDIO_MASTER_EN BIT(30)
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#define QCA8K_MDIO_MASTER_READ BIT(27)
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#define QCA8K_MDIO_MASTER_WRITE 0
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#define QCA8K_MDIO_MASTER_SUP_PRE BIT(26)
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#define QCA8K_MDIO_MASTER_PHY_ADDR(x) ((x) << 21)
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#define QCA8K_MDIO_MASTER_REG_ADDR(x) ((x) << 16)
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#define QCA8K_MDIO_MASTER_DATA(x) (x)
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#define QCA8K_MDIO_MASTER_DATA_MASK GENMASK(15, 0)
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#define QCA8K_MDIO_MASTER_MAX_PORTS 5
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#define QCA8K_MDIO_MASTER_MAX_REG 32
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#define QCA8K_GOL_MAC_ADDR0 0x60
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#define QCA8K_GOL_MAC_ADDR1 0x64
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#define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
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#define QCA8K_PORT_STATUS_SPEED GENMASK(1, 0)
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#define QCA8K_PORT_STATUS_SPEED_10 0
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#define QCA8K_PORT_STATUS_SPEED_100 0x1
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#define QCA8K_PORT_STATUS_SPEED_1000 0x2
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#define QCA8K_PORT_STATUS_TXMAC BIT(2)
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#define QCA8K_PORT_STATUS_RXMAC BIT(3)
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#define QCA8K_PORT_STATUS_TXFLOW BIT(4)
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#define QCA8K_PORT_STATUS_RXFLOW BIT(5)
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#define QCA8K_PORT_STATUS_DUPLEX BIT(6)
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#define QCA8K_PORT_STATUS_LINK_UP BIT(8)
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#define QCA8K_PORT_STATUS_LINK_AUTO BIT(9)
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#define QCA8K_PORT_STATUS_LINK_PAUSE BIT(10)
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#define QCA8K_REG_PORT_HDR_CTRL(_i) (0x9c + (_i * 4))
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#define QCA8K_PORT_HDR_CTRL_RX_MASK GENMASK(3, 2)
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#define QCA8K_PORT_HDR_CTRL_RX_S 2
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#define QCA8K_PORT_HDR_CTRL_TX_MASK GENMASK(1, 0)
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#define QCA8K_PORT_HDR_CTRL_TX_S 0
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#define QCA8K_PORT_HDR_CTRL_ALL 2
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#define QCA8K_PORT_HDR_CTRL_MGMT 1
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#define QCA8K_PORT_HDR_CTRL_NONE 0
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/* EEE control registers */
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#define QCA8K_REG_EEE_CTRL 0x100
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#define QCA8K_REG_EEE_CTRL_LPI_EN(_i) ((_i + 1) * 2)
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/* ACL registers */
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#define QCA8K_REG_PORT_VLAN_CTRL0(_i) (0x420 + (_i * 8))
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#define QCA8K_PORT_VLAN_CVID(x) (x << 16)
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#define QCA8K_PORT_VLAN_SVID(x) x
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#define QCA8K_REG_PORT_VLAN_CTRL1(_i) (0x424 + (_i * 8))
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#define QCA8K_REG_IPV4_PRI_BASE_ADDR 0x470
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#define QCA8K_REG_IPV4_PRI_ADDR_MASK 0x474
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/* Lookup registers */
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#define QCA8K_REG_ATU_DATA0 0x600
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#define QCA8K_ATU_ADDR2_S 24
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#define QCA8K_ATU_ADDR3_S 16
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#define QCA8K_ATU_ADDR4_S 8
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#define QCA8K_REG_ATU_DATA1 0x604
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#define QCA8K_ATU_PORT_M 0x7f
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#define QCA8K_ATU_PORT_S 16
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#define QCA8K_ATU_ADDR0_S 8
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#define QCA8K_REG_ATU_DATA2 0x608
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#define QCA8K_ATU_VID_M 0xfff
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#define QCA8K_ATU_VID_S 8
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#define QCA8K_ATU_STATUS_M 0xf
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#define QCA8K_ATU_STATUS_STATIC 0xf
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#define QCA8K_REG_ATU_FUNC 0x60c
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#define QCA8K_ATU_FUNC_BUSY BIT(31)
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#define QCA8K_ATU_FUNC_PORT_EN BIT(14)
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#define QCA8K_ATU_FUNC_MULTI_EN BIT(13)
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#define QCA8K_ATU_FUNC_FULL BIT(12)
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#define QCA8K_ATU_FUNC_PORT_M 0xf
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#define QCA8K_ATU_FUNC_PORT_S 8
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#define QCA8K_REG_GLOBAL_FW_CTRL0 0x620
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#define QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN BIT(10)
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#define QCA8K_REG_GLOBAL_FW_CTRL1 0x624
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#define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S 24
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#define QCA8K_GLOBAL_FW_CTRL1_BC_DP_S 16
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#define QCA8K_GLOBAL_FW_CTRL1_MC_DP_S 8
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#define QCA8K_GLOBAL_FW_CTRL1_UC_DP_S 0
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#define QCA8K_PORT_LOOKUP_CTRL(_i) (0x660 + (_i) * 0xc)
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#define QCA8K_PORT_LOOKUP_MEMBER GENMASK(6, 0)
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#define QCA8K_PORT_LOOKUP_STATE_MASK GENMASK(18, 16)
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#define QCA8K_PORT_LOOKUP_STATE_DISABLED (0 << 16)
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#define QCA8K_PORT_LOOKUP_STATE_BLOCKING (1 << 16)
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#define QCA8K_PORT_LOOKUP_STATE_LISTENING (2 << 16)
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#define QCA8K_PORT_LOOKUP_STATE_LEARNING (3 << 16)
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#define QCA8K_PORT_LOOKUP_STATE_FORWARD (4 << 16)
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#define QCA8K_PORT_LOOKUP_STATE GENMASK(18, 16)
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#define QCA8K_PORT_LOOKUP_LEARN BIT(20)
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/* Pkt edit registers */
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#define QCA8K_EGRESS_VLAN(x) (0x0c70 + (4 * (x / 2)))
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/* L3 registers */
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#define QCA8K_HROUTER_CONTROL 0xe00
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#define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_M GENMASK(17, 16)
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#define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_S 16
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#define QCA8K_HROUTER_CONTROL_ARP_AGE_MODE 1
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#define QCA8K_HROUTER_PBASED_CONTROL1 0xe08
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#define QCA8K_HROUTER_PBASED_CONTROL2 0xe0c
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#define QCA8K_HNAT_CONTROL 0xe38
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/* MIB registers */
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#define QCA8K_PORT_MIB_COUNTER(_i) (0x1000 + (_i) * 0x100)
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/* QCA specific MII registers */
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#define MII_ATH_MMD_ADDR 0x0d
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#define MII_ATH_MMD_DATA 0x0e
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enum {
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QCA8K_PORT_SPEED_10M = 0,
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QCA8K_PORT_SPEED_100M = 1,
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QCA8K_PORT_SPEED_1000M = 2,
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QCA8K_PORT_SPEED_ERR = 3,
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};
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enum qca8k_fdb_cmd {
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QCA8K_FDB_FLUSH = 1,
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QCA8K_FDB_LOAD = 2,
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QCA8K_FDB_PURGE = 3,
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QCA8K_FDB_NEXT = 6,
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QCA8K_FDB_SEARCH = 7,
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};
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struct ar8xxx_port_status {
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int enabled;
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};
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struct qca8k_priv {
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struct regmap *regmap;
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struct mii_bus *bus;
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struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];
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struct dsa_switch *ds;
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struct mutex reg_mutex;
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struct device *dev;
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struct dsa_switch_ops ops;
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};
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struct qca8k_mib_desc {
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unsigned int size;
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unsigned int offset;
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const char *name;
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};
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struct qca8k_fdb {
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u16 vid;
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u8 port_mask;
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u8 aging;
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u8 mac[6];
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};
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#endif /* __QCA8K_H */
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