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![Rafał Miłecki](/assets/img/avatar_default.png)
kbuild found out that commit 804e27dee4
("bcma: support bringing up
bus hosted on PCIe Gen 2") broke the build on m68k:
drivers/bcma/driver_pcie2.c: In function 'bcma_core_pcie2_up':
>> drivers/bcma/driver_pcie2.c:196:2: error: implicit declaration of function 'pcie_set_readrq' [-Werror\
=implicit-function-declaration]
err = pcie_set_readrq(dev, pcie2->reqsize);
^
cc1: some warnings being treated as errors
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
200 lines
5.6 KiB
C
200 lines
5.6 KiB
C
/*
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* Broadcom specific AMBA
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* PCIe Gen 2 Core
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*
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* Copyright 2014, Broadcom Corporation
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* Copyright 2014, Rafał Miłecki <zajec5@gmail.com>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include "bcma_private.h"
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#include <linux/bcma/bcma.h>
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#include <linux/pci.h>
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/**************************************************
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* R/W ops.
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**************************************************/
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#if 0
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static u32 bcma_core_pcie2_cfg_read(struct bcma_drv_pcie2 *pcie2, u32 addr)
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{
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pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
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pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR);
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return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
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}
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#endif
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static void bcma_core_pcie2_cfg_write(struct bcma_drv_pcie2 *pcie2, u32 addr,
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u32 val)
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{
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pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
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pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, val);
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}
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/**************************************************
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* Init.
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**************************************************/
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static u32 bcma_core_pcie2_war_delay_perst_enab(struct bcma_drv_pcie2 *pcie2,
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bool enable)
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{
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u32 val;
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/* restore back to default */
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val = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
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val |= PCIE2_CLKC_DLYPERST;
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val &= ~PCIE2_CLKC_DISSPROMLD;
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if (enable) {
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val &= ~PCIE2_CLKC_DLYPERST;
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val |= PCIE2_CLKC_DISSPROMLD;
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}
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pcie2_write32(pcie2, (BCMA_CORE_PCIE2_CLK_CONTROL), val);
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/* flush */
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return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
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}
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static void bcma_core_pcie2_set_ltr_vals(struct bcma_drv_pcie2 *pcie2)
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{
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/* LTR0 */
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pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x844);
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pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x883c883c);
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/* LTR1 */
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pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x848);
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pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x88648864);
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/* LTR2 */
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pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x84C);
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pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x90039003);
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}
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static void bcma_core_pcie2_hw_ltr_war(struct bcma_drv_pcie2 *pcie2)
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{
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u8 core_rev = pcie2->core->id.rev;
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u32 devstsctr2;
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if (core_rev < 2 || core_rev == 10 || core_rev > 13)
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return;
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pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
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PCIE2_CAP_DEVSTSCTRL2_OFFSET);
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devstsctr2 = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
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if (devstsctr2 & PCIE2_CAP_DEVSTSCTRL2_LTRENAB) {
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/* force the right LTR values */
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bcma_core_pcie2_set_ltr_vals(pcie2);
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/* TODO:
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si_core_wrapperreg(pcie2, 3, 0x60, 0x8080, 0); */
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/* enable the LTR */
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devstsctr2 |= PCIE2_CAP_DEVSTSCTRL2_LTRENAB;
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pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
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PCIE2_CAP_DEVSTSCTRL2_OFFSET);
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pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, devstsctr2);
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/* set the LTR state to be active */
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pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
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PCIE2_LTR_ACTIVE);
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usleep_range(1000, 2000);
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/* set the LTR state to be sleep */
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pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
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PCIE2_LTR_SLEEP);
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usleep_range(1000, 2000);
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}
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}
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static void pciedev_crwlpciegen2(struct bcma_drv_pcie2 *pcie2)
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{
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u8 core_rev = pcie2->core->id.rev;
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bool pciewar160, pciewar162;
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pciewar160 = core_rev == 7 || core_rev == 9 || core_rev == 11;
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pciewar162 = core_rev == 5 || core_rev == 7 || core_rev == 8 ||
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core_rev == 9 || core_rev == 11;
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if (!pciewar160 && !pciewar162)
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return;
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/* TODO */
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#if 0
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pcie2_set32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL,
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PCIE_DISABLE_L1CLK_GATING);
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#if 0
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pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
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PCIEGEN2_COE_PVT_TL_CTRL_0);
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pcie2_mask32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA,
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~(1 << COE_PVT_TL_CTRL_0_PM_DIS_L1_REENTRY_BIT));
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#endif
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#endif
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}
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static void pciedev_crwlpciegen2_180(struct bcma_drv_pcie2 *pcie2)
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{
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pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_PMCR_REFUP);
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pcie2_set32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x1f);
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}
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static void pciedev_crwlpciegen2_182(struct bcma_drv_pcie2 *pcie2)
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{
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pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_SBMBX);
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pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 1 << 0);
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}
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static void pciedev_reg_pm_clk_period(struct bcma_drv_pcie2 *pcie2)
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{
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struct bcma_drv_cc *drv_cc = &pcie2->core->bus->drv_cc;
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u8 core_rev = pcie2->core->id.rev;
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u32 alp_khz, pm_value;
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if (core_rev <= 13) {
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alp_khz = bcma_pmu_get_alp_clock(drv_cc) / 1000;
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pm_value = (1000000 * 2) / alp_khz;
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pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
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PCIE2_PVT_REG_PM_CLK_PERIOD);
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pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, pm_value);
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}
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}
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void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2)
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{
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struct bcma_bus *bus = pcie2->core->bus;
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struct bcma_chipinfo *ci = &bus->chipinfo;
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u32 tmp;
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tmp = pcie2_read32(pcie2, BCMA_CORE_PCIE2_SPROM(54));
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if ((tmp & 0xe) >> 1 == 2)
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bcma_core_pcie2_cfg_write(pcie2, 0x4e0, 0x17);
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switch (bus->chipinfo.id) {
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case BCMA_CHIP_ID_BCM4360:
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case BCMA_CHIP_ID_BCM4352:
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pcie2->reqsize = 1024;
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break;
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default:
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pcie2->reqsize = 128;
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break;
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}
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if (ci->id == BCMA_CHIP_ID_BCM4360 && ci->rev > 3)
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bcma_core_pcie2_war_delay_perst_enab(pcie2, true);
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bcma_core_pcie2_hw_ltr_war(pcie2);
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pciedev_crwlpciegen2(pcie2);
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pciedev_reg_pm_clk_period(pcie2);
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pciedev_crwlpciegen2_180(pcie2);
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pciedev_crwlpciegen2_182(pcie2);
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}
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/**************************************************
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* Runtime ops.
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**************************************************/
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void bcma_core_pcie2_up(struct bcma_drv_pcie2 *pcie2)
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{
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struct bcma_bus *bus = pcie2->core->bus;
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struct pci_dev *dev = bus->host_pci;
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int err;
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err = pcie_set_readrq(dev, pcie2->reqsize);
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if (err)
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bcma_err(bus, "Error setting PCI_EXP_DEVCTL_READRQ: %d\n", err);
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}
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