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This commit adds files hal/odm_RTL8188E.c, hal/odm_RegConfig8188E.c, hal/rtl8188e_cmd.c, and hal/rtl8188e_dm.c. Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
130 lines
4.1 KiB
C
130 lines
4.1 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#include "odm_precomp.h"
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void odm_ConfigRFReg_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr,
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u32 Data, enum ODM_RF_RADIO_PATH RF_PATH,
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u32 RegAddr)
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{
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if (Addr == 0xffe) {
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ODM_sleep_ms(50);
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} else if (Addr == 0xfd) {
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ODM_delay_ms(5);
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} else if (Addr == 0xfc) {
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ODM_delay_ms(1);
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} else if (Addr == 0xfb) {
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ODM_delay_us(50);
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} else if (Addr == 0xfa) {
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ODM_delay_us(5);
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} else if (Addr == 0xf9) {
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ODM_delay_us(1);
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} else {
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ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
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/* Add 1us delay between BB/RF register setting. */
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ODM_delay_us(1);
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}
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}
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void odm_ConfigRF_RadioA_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Data)
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{
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u32 content = 0x1000; /* RF_Content: radioa_txt */
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u32 maskforPhySet = (u32)(content&0xE000);
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odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet);
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data));
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}
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void odm_ConfigRF_RadioB_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Data)
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{
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u32 content = 0x1001; /* RF_Content: radiob_txt */
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u32 maskforPhySet = (u32)(content&0xE000);
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odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet);
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data));
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}
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void odm_ConfigMAC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u8 Data)
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{
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ODM_Write1Byte(pDM_Odm, Addr, Data);
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data));
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}
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void odm_ConfigBB_AGC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data)
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{
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ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
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/* Add 1us delay between BB/RF register setting. */
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ODM_delay_us(1);
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
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("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n",
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Addr, Data));
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}
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void odm_ConfigBB_PHY_REG_PG_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr,
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u32 Bitmask, u32 Data)
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{
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if (Addr == 0xfe) {
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ODM_sleep_ms(50);
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} else if (Addr == 0xfd) {
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ODM_delay_ms(5);
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} else if (Addr == 0xfc) {
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ODM_delay_ms(1);
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} else if (Addr == 0xfb) {
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ODM_delay_us(50);
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} else if (Addr == 0xfa) {
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ODM_delay_us(5);
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} else if (Addr == 0xf9) {
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ODM_delay_us(1);
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} else{
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD,
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("===> @@@@@@@ ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n",
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Addr, Bitmask, Data));
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storePwrIndexDiffRateOffset(pDM_Odm->Adapter, Addr, Bitmask, Data);
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}
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}
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void odm_ConfigBB_PHY_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data)
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{
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if (Addr == 0xfe) {
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ODM_sleep_ms(50);
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} else if (Addr == 0xfd) {
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ODM_delay_ms(5);
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} else if (Addr == 0xfc) {
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ODM_delay_ms(1);
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} else if (Addr == 0xfb) {
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ODM_delay_us(50);
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} else if (Addr == 0xfa) {
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ODM_delay_us(5);
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} else if (Addr == 0xf9) {
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ODM_delay_us(1);
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} else {
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if (Addr == 0xa24)
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pDM_Odm->RFCalibrateInfo.RegA24 = Data;
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ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
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/* Add 1us delay between BB/RF register setting. */
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ODM_delay_us(1);
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
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("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n",
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Addr, Data));
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}
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}
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