mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-02 15:18:19 +00:00
68a32ba141
- printk fourcc modifier support added %p4cc core: - drm_crtc_commit_wait - atomic plane state helpers reworked for full state - dma-buf heaps API rework - edid: rework and improvements for displayid dp-mst: - better topology logging bridge: - Chipone ICN6211 - Lontium LT8912B - anx7625 regulator support panel: - fix lt9611 4k panels handling simple-kms: - add plane state helpers ttm: - debugfs support - removal of unused sysfs - ignore signaled moved fences - ioremap buffer according to mem caching i915: - Alderlake S enablement - Conversion to dma_resv_locking - Bring back watchdog timeout support - legacy ioctl cleanups - add GEM TDDO and RFC process - DG1 LMEM preparation work - intel_display.c refactoring - Gen9/TGL PCH combination support - eDP MSO Support - multiple PSR instance support - Link training debug updates - Disable PSR2 support on JSL/EHL - DDR5/LPDDR5 support for bw calcs - LSPCON limited to gen9/10 platforms - HSW/BDW async flip/VTd corruption workaround = SAGV watermakr fixes - SNB hard hang on ring resume fix - Limit imported dma-buf size - move to use new tasklet API - refactor KBL/TGL/ADL-S display/gt steppings - refactoring legacy DP/HDMI, FB plane code out amdgpu: - uapi: add ioctl to query video capabilities - Iniital AMD Freesync HDMI support - Initial Adebaran support - 10bpc dithering improvements - DCN secure display support - Drop legacy IO BAR requirements - PCIE/S0ix/RAS/Prime/Reset fixes - Display ASSR support - SMU gfx busy queues for RV/PCO - Initial LTTPR display work amdkfd: - MMU notifier fixes - APU fixes radeon: - debugfs cleanps - fw error handling ifix - Flexible array cleanups msm: - big DSI phy/pll cleanup - sc7280 initial support - commong bandwidth scaling path - shrinker locking contention fixes - unpin/swap support for GEM objcets ast: - cursor plane handling reworked tegra: - don't register DP AUX channels before connectors zynqmp: - fix OOB struct padding memset gma500: - drop ttm and medfield support exynos: - request_irq cleanup function mediatek: - fine tune line time for EOTp - MT8192 dpi support - atomic crtc config updates - don't support HDMI connector creation mxsdb: - imx8mm support panfrost: -= MMU IRQ handling rework qxl: - locking fixes - resource deallocation changes sun4i: - add alpha properties to UI/VI layers vc4: - RPi4 CEC support vmwgfx: - doc cleanups arc: - moved to drm/tiny -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJgiNSVAAoJEAx081l5xIa+fvYP/1206BfOYOx5opt5K3By06ZY zrOsbeaqFdHzfUR7xVwO4vqQNhkX4Pt8H/U7uYZx8PRdrXzGENwWLIaIskyUrKOd BtwNqUr0ZXJGDlGg26StnUHKeAXuYXlpBKLta5y4LUTkI+bm6V/oVaDMq4dnah70 2CXS4C2mnaFRLBzuRlraxoGFN4eZkz6Waeyo6PJxn/l2GE2gw+jho0Yrh8e8F2w5 EjQeNF22/uHwznov03XFJlyugecuBDbE8A6Ma/znnkVdBXcT94eUMugbKOKi4Nn6 PuJOEdJxmj/9s3oi6kBERc8dvpOj0O+8Vp+xOzn2U3BVXebvu7VoJsq6FcAvL5lN ltj4iErxUlEud2GRIVUMx8OTFiKj4ThRFJ2/8Uf22r3P7RHO5E9BLnZBzqIAhDVr s2cDBMItcxcVHRCmE04h12XAO4libZBb2TVjbqG94Acq7beR76pMszFrmxPmHBEm NGe1s7+ajxMzsq/NIsk4XAhqSmJo6+ujKyyVnrgvKUVeEaWW1U4YvjhJaetnP4fB 47gF24wOSNFwiCUZlqaIpp/MR4Z8YmaJ7tayWQq4Oj/neWe/yc8xQgQIuE8GL20j P9eNQNvlBnoxkz275M9x4kVhJ5FRjr7OYnd3sFVnALuj6fnL3Z1RXLqI1lNtIz1d YM89veZuNxMaiDz8roPH =bLWZ -----END PGP SIGNATURE----- Merge tag 'drm-next-2021-04-28' of git://anongit.freedesktop.org/drm/drm Pull drm updates from Dave Airlie: "The usual lots of work all over the place. i915 has gotten some Alderlake work and prelim DG1 code, along with a major locking rework over the GEM code, and brings back the property of timing out long running jobs using a watchdog. amdgpu has some Alderbran support (new GPU), freesync HDMI support along with a lot other fixes. Outside of the drm, there is a new printf specifier added which should have all the correct acks/sobs: - printk fourcc modifier support added %p4cc Summary: core: - drm_crtc_commit_wait - atomic plane state helpers reworked for full state - dma-buf heaps API rework - edid: rework and improvements for displayid dp-mst: - better topology logging bridge: - Chipone ICN6211 - Lontium LT8912B - anx7625 regulator support panel: - fix lt9611 4k panels handling simple-kms: - add plane state helpers ttm: - debugfs support - removal of unused sysfs - ignore signaled moved fences - ioremap buffer according to mem caching i915: - Alderlake S enablement - Conversion to dma_resv_locking - Bring back watchdog timeout support - legacy ioctl cleanups - add GEM TDDO and RFC process - DG1 LMEM preparation work - intel_display.c refactoring - Gen9/TGL PCH combination support - eDP MSO Support - multiple PSR instance support - Link training debug updates - Disable PSR2 support on JSL/EHL - DDR5/LPDDR5 support for bw calcs - LSPCON limited to gen9/10 platforms - HSW/BDW async flip/VTd corruption workaround - SAGV watermark fixes - SNB hard hang on ring resume fix - Limit imported dma-buf size - move to use new tasklet API - refactor KBL/TGL/ADL-S display/gt steppings - refactoring legacy DP/HDMI, FB plane code out amdgpu: - uapi: add ioctl to query video capabilities - Iniital AMD Freesync HDMI support - Initial Adebaran support - 10bpc dithering improvements - DCN secure display support - Drop legacy IO BAR requirements - PCIE/S0ix/RAS/Prime/Reset fixes - Display ASSR support - SMU gfx busy queues for RV/PCO - Initial LTTPR display work amdkfd: - MMU notifier fixes - APU fixes radeon: - debugfs cleanps - fw error handling ifix - Flexible array cleanups msm: - big DSI phy/pll cleanup - sc7280 initial support - commong bandwidth scaling path - shrinker locking contention fixes - unpin/swap support for GEM objcets ast: - cursor plane handling reworked tegra: - don't register DP AUX channels before connectors zynqmp: - fix OOB struct padding memset gma500: - drop ttm and medfield support exynos: - request_irq cleanup function mediatek: - fine tune line time for EOTp - MT8192 dpi support - atomic crtc config updates - don't support HDMI connector creation mxsdb: - imx8mm support panfrost: - MMU IRQ handling rework qxl: - locking fixes - resource deallocation changes sun4i: - add alpha properties to UI/VI layers vc4: - RPi4 CEC support vmwgfx: - doc cleanups arc: - moved to drm/tiny" * tag 'drm-next-2021-04-28' of git://anongit.freedesktop.org/drm/drm: (1390 commits) drm/ttm: Don't count pages in SG BOs against pages_limit drm/ttm: fix return value check drm/bridge: lt8912b: fix incorrect handling of of_* return values drm: bridge: fix LONTIUM use of mipi_dsi_() functions drm: bridge: fix ANX7625 use of mipi_dsi_() functions drm/amdgpu: page retire over debugfs mechanism drm/radeon: Fix a missing check bug in radeon_dp_mst_detect() drm/amd/display: Fix the Wunused-function warning drm/radeon/r600: Fix variables that are not used after assignment drm/amdgpu/smu7: fix CAC setting on TOPAZ drm/amd/display: Update DCN302 SR Exit Latency drm/amdgpu: enable ras eeprom on aldebaran drm/amdgpu: RAS harvest on driver load drm/amdgpu: add ras aldebaran ras eeprom driver drm/amd/pm: increase time out value when sending msg to SMU drm/amdgpu: add DMUB outbox event IRQ source define/complete/debug flag drm/amd/pm: add the callback to get vbios bootup values for vangogh drm/radeon: Fix size overflow drm/amdgpu: Fix size overflow drm/amdgpu: move mmhub ras_func init to ip specific file ...
300 lines
7.6 KiB
C
300 lines
7.6 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#include <linux/list.h>
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#include <linux/list_sort.h>
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#include <linux/llist.h>
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#include "i915_drv.h"
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#include "intel_engine.h"
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#include "intel_engine_user.h"
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#include "intel_gt.h"
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struct intel_engine_cs *
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intel_engine_lookup_user(struct drm_i915_private *i915, u8 class, u8 instance)
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{
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struct rb_node *p = i915->uabi_engines.rb_node;
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while (p) {
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struct intel_engine_cs *it =
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rb_entry(p, typeof(*it), uabi_node);
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if (class < it->uabi_class)
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p = p->rb_left;
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else if (class > it->uabi_class ||
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instance > it->uabi_instance)
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p = p->rb_right;
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else if (instance < it->uabi_instance)
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p = p->rb_left;
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else
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return it;
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}
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return NULL;
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}
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void intel_engine_add_user(struct intel_engine_cs *engine)
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{
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llist_add((struct llist_node *)&engine->uabi_node,
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(struct llist_head *)&engine->i915->uabi_engines);
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}
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static const u8 uabi_classes[] = {
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[RENDER_CLASS] = I915_ENGINE_CLASS_RENDER,
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[COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY,
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[VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO,
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[VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,
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};
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static int engine_cmp(void *priv, const struct list_head *A,
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const struct list_head *B)
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{
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const struct intel_engine_cs *a =
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container_of((struct rb_node *)A, typeof(*a), uabi_node);
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const struct intel_engine_cs *b =
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container_of((struct rb_node *)B, typeof(*b), uabi_node);
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if (uabi_classes[a->class] < uabi_classes[b->class])
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return -1;
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if (uabi_classes[a->class] > uabi_classes[b->class])
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return 1;
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if (a->instance < b->instance)
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return -1;
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if (a->instance > b->instance)
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return 1;
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return 0;
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}
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static struct llist_node *get_engines(struct drm_i915_private *i915)
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{
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return llist_del_all((struct llist_head *)&i915->uabi_engines);
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}
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static void sort_engines(struct drm_i915_private *i915,
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struct list_head *engines)
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{
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struct llist_node *pos, *next;
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llist_for_each_safe(pos, next, get_engines(i915)) {
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struct intel_engine_cs *engine =
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container_of((struct rb_node *)pos, typeof(*engine),
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uabi_node);
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list_add((struct list_head *)&engine->uabi_node, engines);
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}
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list_sort(NULL, engines, engine_cmp);
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}
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static void set_scheduler_caps(struct drm_i915_private *i915)
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{
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static const struct {
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u8 engine;
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u8 sched;
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} map[] = {
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#define MAP(x, y) { ilog2(I915_ENGINE_##x), ilog2(I915_SCHEDULER_CAP_##y) }
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MAP(HAS_PREEMPTION, PREEMPTION),
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MAP(HAS_SEMAPHORES, SEMAPHORES),
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MAP(SUPPORTS_STATS, ENGINE_BUSY_STATS),
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#undef MAP
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};
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struct intel_engine_cs *engine;
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u32 enabled, disabled;
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enabled = 0;
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disabled = 0;
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for_each_uabi_engine(engine, i915) { /* all engines must agree! */
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int i;
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if (engine->schedule)
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enabled |= (I915_SCHEDULER_CAP_ENABLED |
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I915_SCHEDULER_CAP_PRIORITY);
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else
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disabled |= (I915_SCHEDULER_CAP_ENABLED |
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I915_SCHEDULER_CAP_PRIORITY);
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for (i = 0; i < ARRAY_SIZE(map); i++) {
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if (engine->flags & BIT(map[i].engine))
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enabled |= BIT(map[i].sched);
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else
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disabled |= BIT(map[i].sched);
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}
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}
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i915->caps.scheduler = enabled & ~disabled;
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if (!(i915->caps.scheduler & I915_SCHEDULER_CAP_ENABLED))
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i915->caps.scheduler = 0;
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}
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const char *intel_engine_class_repr(u8 class)
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{
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static const char * const uabi_names[] = {
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[RENDER_CLASS] = "rcs",
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[COPY_ENGINE_CLASS] = "bcs",
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[VIDEO_DECODE_CLASS] = "vcs",
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[VIDEO_ENHANCEMENT_CLASS] = "vecs",
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};
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if (class >= ARRAY_SIZE(uabi_names) || !uabi_names[class])
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return "xxx";
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return uabi_names[class];
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}
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struct legacy_ring {
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struct intel_gt *gt;
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u8 class;
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u8 instance;
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};
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static int legacy_ring_idx(const struct legacy_ring *ring)
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{
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static const struct {
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u8 base, max;
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} map[] = {
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[RENDER_CLASS] = { RCS0, 1 },
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[COPY_ENGINE_CLASS] = { BCS0, 1 },
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[VIDEO_DECODE_CLASS] = { VCS0, I915_MAX_VCS },
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[VIDEO_ENHANCEMENT_CLASS] = { VECS0, I915_MAX_VECS },
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};
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if (GEM_DEBUG_WARN_ON(ring->class >= ARRAY_SIZE(map)))
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return INVALID_ENGINE;
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if (GEM_DEBUG_WARN_ON(ring->instance >= map[ring->class].max))
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return INVALID_ENGINE;
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return map[ring->class].base + ring->instance;
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}
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static void add_legacy_ring(struct legacy_ring *ring,
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struct intel_engine_cs *engine)
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{
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if (engine->gt != ring->gt || engine->class != ring->class) {
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ring->gt = engine->gt;
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ring->class = engine->class;
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ring->instance = 0;
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}
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engine->legacy_idx = legacy_ring_idx(ring);
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if (engine->legacy_idx != INVALID_ENGINE)
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ring->instance++;
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}
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void intel_engines_driver_register(struct drm_i915_private *i915)
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{
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struct legacy_ring ring = {};
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u8 uabi_instances[4] = {};
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struct list_head *it, *next;
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struct rb_node **p, *prev;
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LIST_HEAD(engines);
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sort_engines(i915, &engines);
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prev = NULL;
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p = &i915->uabi_engines.rb_node;
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list_for_each_safe(it, next, &engines) {
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struct intel_engine_cs *engine =
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container_of((struct rb_node *)it, typeof(*engine),
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uabi_node);
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char old[sizeof(engine->name)];
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if (intel_gt_has_unrecoverable_error(engine->gt))
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continue; /* ignore incomplete engines */
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GEM_BUG_ON(engine->class >= ARRAY_SIZE(uabi_classes));
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engine->uabi_class = uabi_classes[engine->class];
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GEM_BUG_ON(engine->uabi_class >= ARRAY_SIZE(uabi_instances));
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engine->uabi_instance = uabi_instances[engine->uabi_class]++;
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/* Replace the internal name with the final user facing name */
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memcpy(old, engine->name, sizeof(engine->name));
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scnprintf(engine->name, sizeof(engine->name), "%s%u",
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intel_engine_class_repr(engine->class),
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engine->uabi_instance);
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DRM_DEBUG_DRIVER("renamed %s to %s\n", old, engine->name);
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rb_link_node(&engine->uabi_node, prev, p);
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rb_insert_color(&engine->uabi_node, &i915->uabi_engines);
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GEM_BUG_ON(intel_engine_lookup_user(i915,
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engine->uabi_class,
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engine->uabi_instance) != engine);
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/* Fix up the mapping to match default execbuf::user_map[] */
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add_legacy_ring(&ring, engine);
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prev = &engine->uabi_node;
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p = &prev->rb_right;
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}
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if (IS_ENABLED(CONFIG_DRM_I915_SELFTESTS) &&
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IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) {
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struct intel_engine_cs *engine;
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unsigned int isolation;
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int class, inst;
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int errors = 0;
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for (class = 0; class < ARRAY_SIZE(uabi_instances); class++) {
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for (inst = 0; inst < uabi_instances[class]; inst++) {
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engine = intel_engine_lookup_user(i915,
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class, inst);
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if (!engine) {
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pr_err("UABI engine not found for { class:%d, instance:%d }\n",
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class, inst);
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errors++;
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continue;
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}
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if (engine->uabi_class != class ||
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engine->uabi_instance != inst) {
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pr_err("Wrong UABI engine:%s { class:%d, instance:%d } found for { class:%d, instance:%d }\n",
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engine->name,
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engine->uabi_class,
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engine->uabi_instance,
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class, inst);
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errors++;
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continue;
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}
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}
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}
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/*
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* Make sure that classes with multiple engine instances all
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* share the same basic configuration.
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*/
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isolation = intel_engines_has_context_isolation(i915);
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for_each_uabi_engine(engine, i915) {
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unsigned int bit = BIT(engine->uabi_class);
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unsigned int expected = engine->default_state ? bit : 0;
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if ((isolation & bit) != expected) {
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pr_err("mismatching default context state for class %d on engine %s\n",
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engine->uabi_class, engine->name);
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errors++;
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}
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}
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if (drm_WARN(&i915->drm, errors,
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"Invalid UABI engine mapping found"))
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i915->uabi_engines = RB_ROOT;
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}
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set_scheduler_caps(i915);
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}
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unsigned int intel_engines_has_context_isolation(struct drm_i915_private *i915)
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{
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struct intel_engine_cs *engine;
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unsigned int which;
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which = 0;
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for_each_uabi_engine(engine, i915)
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if (engine->default_state)
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which |= BIT(engine->uabi_class);
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return which;
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}
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