171 lines
3.8 KiB
C
171 lines
3.8 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_GT_TYPES__
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#define __INTEL_GT_TYPES__
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#include <linux/ktime.h>
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#include <linux/list.h>
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#include <linux/llist.h>
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#include <linux/mutex.h>
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#include <linux/notifier.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <linux/workqueue.h>
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#include "uc/intel_uc.h"
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#include "i915_vma.h"
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#include "intel_engine_types.h"
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#include "intel_gt_buffer_pool_types.h"
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#include "intel_llc_types.h"
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#include "intel_reset_types.h"
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#include "intel_rc6_types.h"
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#include "intel_rps_types.h"
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#include "intel_wakeref.h"
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struct drm_i915_private;
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struct i915_ggtt;
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struct intel_engine_cs;
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struct intel_uncore;
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struct intel_gt {
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struct drm_i915_private *i915;
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struct intel_uncore *uncore;
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struct i915_ggtt *ggtt;
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struct intel_uc uc;
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struct intel_gt_timelines {
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spinlock_t lock; /* protects active_list */
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struct list_head active_list;
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} timelines;
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struct intel_gt_requests {
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/**
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* We leave the user IRQ off as much as possible,
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* but this means that requests will finish and never
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* be retired once the system goes idle. Set a timer to
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* fire periodically while the ring is running. When it
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* fires, go retire requests.
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*/
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struct delayed_work retire_work;
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} requests;
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struct {
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struct llist_head list;
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struct work_struct work;
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} watchdog;
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struct intel_wakeref wakeref;
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atomic_t user_wakeref;
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struct list_head closed_vma;
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spinlock_t closed_lock; /* guards the list of closed_vma */
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ktime_t last_init_time;
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struct intel_reset reset;
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/**
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* Is the GPU currently considered idle, or busy executing
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* userspace requests? Whilst idle, we allow runtime power
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* management to power down the hardware and display clocks.
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* In order to reduce the effect on performance, there
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* is a slight delay before we do so.
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*/
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intel_wakeref_t awake;
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u32 clock_frequency;
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u32 clock_period_ns;
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struct intel_llc llc;
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struct intel_rc6 rc6;
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struct intel_rps rps;
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spinlock_t irq_lock;
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u32 gt_imr;
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u32 pm_ier;
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u32 pm_imr;
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u32 pm_guc_events;
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struct {
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bool active;
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/**
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* @lock: Lock protecting the below fields.
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*/
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seqcount_mutex_t lock;
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/**
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* @total: Total time this engine was busy.
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*
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* Accumulated time not counting the most recent block in cases
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* where engine is currently busy (active > 0).
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*/
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ktime_t total;
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/**
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* @start: Timestamp of the last idle to active transition.
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*
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* Idle is defined as active == 0, active is active > 0.
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*/
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ktime_t start;
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} stats;
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struct intel_engine_cs *engine[I915_NUM_ENGINES];
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struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
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[MAX_ENGINE_INSTANCE + 1];
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/*
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* Default address space (either GGTT or ppGTT depending on arch).
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*
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* Reserved for exclusive use by the kernel.
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*/
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struct i915_address_space *vm;
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/*
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* A pool of objects to use as shadow copies of client batch buffers
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* when the command parser is enabled. Prevents the client from
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* modifying the batch contents after software parsing.
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*
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* Buffers older than 1s are periodically reaped from the pool,
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* or may be reclaimed by the shrinker before then.
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*/
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struct intel_gt_buffer_pool buffer_pool;
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struct i915_vma *scratch;
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struct intel_gt_info {
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intel_engine_mask_t engine_mask;
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u8 num_engines;
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/* Media engine access to SFC per instance */
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u8 vdbox_sfc_access;
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/* Slice/subslice/EU info */
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struct sseu_dev_info sseu;
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} info;
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};
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enum intel_gt_scratch_field {
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/* 8 bytes */
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INTEL_GT_SCRATCH_FIELD_DEFAULT = 0,
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/* 8 bytes */
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INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH = 128,
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/* 8 bytes */
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INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256,
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/* 6 * 8 bytes */
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INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR = 2048,
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/* 4 bytes */
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INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1 = 2096,
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};
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#endif /* __INTEL_GT_TYPES_H__ */
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