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![Linus Torvalds](/assets/img/avatar_default.png)
- Merged in a branch of irqchip changes from Thomas Gleixner: we need to have new callbacks from the irqchip to determine if the GPIO line will be eligible for IRQs, and this callback must be able to say "no". After some thinking I got the branch from tglx and have switched all current users over to use this. - Based on tglx patches, we have added some generic irqchip helpers in the gpiolib core. These will help centralize code when GPIO drivers have simple chained/cascaded IRQs. Drivers will still define their irqchip vtables, but the gpiolib core will take care of irqdomain set-up, mapping from local offsets to Linux irqs, and reserve resources by marking the GPIO lines for IRQs. - Initially the PL061 and Nomadik GPIO/pin control drivers have been switched over to use the new gpiochip-to-irqchip infrastructure with more drivers expected for the next kernel cycle. The factoring of just two drivers still makes it worth it so it is already a win. - A new driver for the Synopsys DesignWare APB GPIO block. - Modify the DaVinci GPIO driver to be reusable also for the new TI Keystone architecture. - A new driver for the LSI ZEVIO SoCs. - Delete the obsolte tnetv107x driver. - Some incremental work on GPIO descriptors: have gpiod_direction_output() use a logical level, respecting assertion polarity through ACTIVE_LOW flags, adding gpiod_direction_output_raw() for the case where you want to set that very value. Add gpiochip_get_desc() to fetch a GPIO descriptor from a specific offset on a certain chip inside driver code. - Switch ACPI GPIO code over to using gpiochip_get_desc() and get rid of gpio_to_desc(). - The ACPI GPIO event handling code has been reworked after encountering an actual real life implementation. - Support for ACPI GPIO operation regions. - Generic GPIO chips can now be assigned labels/names from platform data. - We now clamp values returned from GPIO drivers to the boolean [0,1] range. - Some improved documentation on how to use the polarity flag was added. - The a large slew of incremental driver updates and non-critical fixes. Some targeted for stable. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJTPQnkAAoJEEEQszewGV1zyf4P/AmXV0O/FoyeQnXDxDsp7V/t JpfD0Gy8FlFmRxjG+UYutRCWUHxFQJU+j0ToVC4/N8clNS1LwA+ZwhNgB8dqRokz JVeeqUPn95z2kGe3j9DgVXWMRAytq7y8fXFuNUN36losceuxyOj4mYKLP9Yjnp9l 4pS1TtQHF95a7qmnyYjGZy8VNcUz1gJ7wJrGxKI+Kl/8pcdA6rPqom6ozCXpZjaD 5GGQoSvXKIn44+8qZeJsebd1YEso/8K66e9JomcGEsuZl78ArDOzoSllpYF2h/RM bo4BFUmoOL3/jVp7FFVbybfolwuRmQesY4NFqx03e+y++hxHFHl90FT+mnednS2Q k4lB0o1YRjf2tfMmm4cJ3tVBnFRhssTVb9ynDbzUw61mNVEuxP90f/njrHlObnPT 1uVVWUE+4ojral213S2IYGHkg1OlWSn0DP6tEaswjOsGJrMdXpdxS5RPwcRtcByT HufZRNbUbLzXBzf4WeV2foSS3XqbXYcuMfdRBSWrbuJqW56robbdKKyvrMRPvh7j FV7SEK0yFPRe3nuzKM+t9TDGdUt4qivv/YfVeGfCnTVgFOac6cKrHG9gzM58mVcb 4czG3B1TbqgfGVeZuew4qUdlHSmnSsS+pf/h9Yh9QCHqaKGh3R17cSDxIKAIVTIW pH6nuShTXsbrmRMeMhux =8Qqf -----END PGP SIGNATURE----- Merge tag 'gpio-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio Pull bulk of gpio updates from Linus Walleij: "A pretty big chunk of changes this time, but it has all been on rotation in linux-next and had some testing. Of course there will be some amount of fixes on top... - Merged in a branch of irqchip changes from Thomas Gleixner: we need to have new callbacks from the irqchip to determine if the GPIO line will be eligible for IRQs, and this callback must be able to say "no". After some thinking I got the branch from tglx and have switched all current users over to use this. - Based on tglx patches, we have added some generic irqchip helpers in the gpiolib core. These will help centralize code when GPIO drivers have simple chained/cascaded IRQs. Drivers will still define their irqchip vtables, but the gpiolib core will take care of irqdomain set-up, mapping from local offsets to Linux irqs, and reserve resources by marking the GPIO lines for IRQs. - Initially the PL061 and Nomadik GPIO/pin control drivers have been switched over to use the new gpiochip-to-irqchip infrastructure with more drivers expected for the next kernel cycle. The factoring of just two drivers still makes it worth it so it is already a win. - A new driver for the Synopsys DesignWare APB GPIO block. - Modify the DaVinci GPIO driver to be reusable also for the new TI Keystone architecture. - A new driver for the LSI ZEVIO SoCs. - Delete the obsolte tnetv107x driver. - Some incremental work on GPIO descriptors: have gpiod_direction_output() use a logical level, respecting assertion polarity through ACTIVE_LOW flags, adding gpiod_direction_output_raw() for the case where you want to set that very value. Add gpiochip_get_desc() to fetch a GPIO descriptor from a specific offset on a certain chip inside driver code. - Switch ACPI GPIO code over to using gpiochip_get_desc() and get rid of gpio_to_desc(). - The ACPI GPIO event handling code has been reworked after encountering an actual real life implementation. - Support for ACPI GPIO operation regions. - Generic GPIO chips can now be assigned labels/names from platform data. - We now clamp values returned from GPIO drivers to the boolean [0,1] range. - Some improved documentation on how to use the polarity flag was added. - a large slew of incremental driver updates and non-critical fixes. Some targeted for stable" * tag 'gpio-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (80 commits) gpio: rcar: Add helper variable dev = &pdev->dev gpio-lynxpoint: force gpio_get() to return "1" and "0" only gpio: unmap gpio irqs properly pch_gpio: set value before enabling output direction gpio: moxart: Actually set output state in moxart_gpio_direction_output() gpio: moxart: Avoid forward declaration gpio: mxs: Allow for recursive enable_irq_wake() call gpio: samsung: Add missing "break" statement gpio: twl4030: Remove redundant assignment gpio: dwapb: correct gpio-cells in binding document gpio: iop: fix devm_ioremap_resource() return value checking pinctrl: coh901: convert driver to use gpiolib irqchip pinctrl: nomadik: convert driver to use gpiolib irqchip gpio: pl061: convert driver to use gpiolib irqchip gpio: add IRQ chip helpers in gpiolib pinctrl: nomadik: factor in platform data container pinctrl: nomadik: rename secondary to latent gpio: Driver for SYSCON-based GPIOs gpio: generic: Use platform_device_id->driver_data field for driver flags pinctrl: coh901: move irq line locking to resource callbacks ...
608 lines
15 KiB
C
608 lines
15 KiB
C
/*
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* Pinctrl GPIO driver for Intel Baytrail
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* Copyright (c) 2012-2013, Intel Corporation.
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*
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* Author: Mathias Nyman <mathias.nyman@linux.intel.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/bitops.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/gpio.h>
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#include <linux/irqdomain.h>
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#include <linux/acpi.h>
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#include <linux/platform_device.h>
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#include <linux/seq_file.h>
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#include <linux/io.h>
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#include <linux/pm_runtime.h>
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#include <linux/pinctrl/pinctrl.h>
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/* memory mapped register offsets */
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#define BYT_CONF0_REG 0x000
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#define BYT_CONF1_REG 0x004
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#define BYT_VAL_REG 0x008
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#define BYT_DFT_REG 0x00c
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#define BYT_INT_STAT_REG 0x800
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/* BYT_CONF0_REG register bits */
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#define BYT_TRIG_NEG BIT(26)
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#define BYT_TRIG_POS BIT(25)
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#define BYT_TRIG_LVL BIT(24)
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#define BYT_PIN_MUX 0x07
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/* BYT_VAL_REG register bits */
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#define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/
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#define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/
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#define BYT_LEVEL BIT(0)
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#define BYT_DIR_MASK (BIT(1) | BIT(2))
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#define BYT_TRIG_MASK (BIT(26) | BIT(25) | BIT(24))
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#define BYT_NGPIO_SCORE 102
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#define BYT_NGPIO_NCORE 28
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#define BYT_NGPIO_SUS 44
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#define BYT_SCORE_ACPI_UID "1"
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#define BYT_NCORE_ACPI_UID "2"
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#define BYT_SUS_ACPI_UID "3"
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/*
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* Baytrail gpio controller consist of three separate sub-controllers called
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* SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID.
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*
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* GPIO numbering is _not_ ordered meaning that gpio # 0 in ACPI namespace does
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* _not_ correspond to the first gpio register at controller's gpio base.
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* There is no logic or pattern in mapping gpio numbers to registers (pads) so
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* each sub-controller needs to have its own mapping table
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*/
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/* score_pins[gpio_nr] = pad_nr */
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static unsigned const score_pins[BYT_NGPIO_SCORE] = {
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85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
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36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
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54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
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52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
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95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
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86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
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80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
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2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
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31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
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24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
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97, 100,
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};
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static unsigned const ncore_pins[BYT_NGPIO_NCORE] = {
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19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
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14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
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3, 6, 10, 13, 2, 5, 9, 7,
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};
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static unsigned const sus_pins[BYT_NGPIO_SUS] = {
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29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
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18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
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0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
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26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
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52, 53, 59, 40,
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};
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static struct pinctrl_gpio_range byt_ranges[] = {
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{
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.name = BYT_SCORE_ACPI_UID, /* match with acpi _UID in probe */
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.npins = BYT_NGPIO_SCORE,
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.pins = score_pins,
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},
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{
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.name = BYT_NCORE_ACPI_UID,
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.npins = BYT_NGPIO_NCORE,
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.pins = ncore_pins,
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},
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{
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.name = BYT_SUS_ACPI_UID,
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.npins = BYT_NGPIO_SUS,
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.pins = sus_pins,
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},
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{
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},
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};
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struct byt_gpio {
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struct gpio_chip chip;
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struct irq_domain *domain;
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struct platform_device *pdev;
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spinlock_t lock;
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void __iomem *reg_base;
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struct pinctrl_gpio_range *range;
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};
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#define to_byt_gpio(c) container_of(c, struct byt_gpio, chip)
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static void __iomem *byt_gpio_reg(struct gpio_chip *chip, unsigned offset,
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int reg)
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{
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struct byt_gpio *vg = to_byt_gpio(chip);
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u32 reg_offset;
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if (reg == BYT_INT_STAT_REG)
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reg_offset = (offset / 32) * 4;
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else
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reg_offset = vg->range->pins[offset] * 16;
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return vg->reg_base + reg_offset + reg;
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}
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static bool is_special_pin(struct byt_gpio *vg, unsigned offset)
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{
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/* SCORE pin 92-93 */
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if (!strcmp(vg->range->name, BYT_SCORE_ACPI_UID) &&
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offset >= 92 && offset <= 93)
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return true;
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/* SUS pin 11-21 */
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if (!strcmp(vg->range->name, BYT_SUS_ACPI_UID) &&
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offset >= 11 && offset <= 21)
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return true;
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return false;
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}
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static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
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{
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struct byt_gpio *vg = to_byt_gpio(chip);
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void __iomem *reg = byt_gpio_reg(chip, offset, BYT_CONF0_REG);
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u32 value;
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bool special;
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/*
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* In most cases, func pin mux 000 means GPIO function.
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* But, some pins may have func pin mux 001 represents
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* GPIO function. Only allow user to export pin with
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* func pin mux preset as GPIO function by BIOS/FW.
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*/
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value = readl(reg) & BYT_PIN_MUX;
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special = is_special_pin(vg, offset);
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if ((special && value != 1) || (!special && value)) {
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dev_err(&vg->pdev->dev,
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"pin %u cannot be used as GPIO.\n", offset);
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return -EINVAL;
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}
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pm_runtime_get(&vg->pdev->dev);
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return 0;
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}
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static void byt_gpio_free(struct gpio_chip *chip, unsigned offset)
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{
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struct byt_gpio *vg = to_byt_gpio(chip);
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void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
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u32 value;
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/* clear interrupt triggering */
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value = readl(reg);
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value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
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writel(value, reg);
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pm_runtime_put(&vg->pdev->dev);
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}
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static int byt_irq_type(struct irq_data *d, unsigned type)
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{
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struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
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u32 offset = irqd_to_hwirq(d);
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u32 value;
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unsigned long flags;
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void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
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if (offset >= vg->chip.ngpio)
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return -EINVAL;
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spin_lock_irqsave(&vg->lock, flags);
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value = readl(reg);
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/* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
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* are used to indicate high and low level triggering
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*/
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value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
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switch (type) {
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case IRQ_TYPE_LEVEL_HIGH:
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value |= BYT_TRIG_LVL;
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case IRQ_TYPE_EDGE_RISING:
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value |= BYT_TRIG_POS;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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value |= BYT_TRIG_LVL;
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case IRQ_TYPE_EDGE_FALLING:
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value |= BYT_TRIG_NEG;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
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break;
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}
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writel(value, reg);
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spin_unlock_irqrestore(&vg->lock, flags);
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return 0;
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}
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static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
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return readl(reg) & BYT_LEVEL;
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}
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static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct byt_gpio *vg = to_byt_gpio(chip);
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void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
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unsigned long flags;
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u32 old_val;
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spin_lock_irqsave(&vg->lock, flags);
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old_val = readl(reg);
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if (value)
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writel(old_val | BYT_LEVEL, reg);
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else
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writel(old_val & ~BYT_LEVEL, reg);
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spin_unlock_irqrestore(&vg->lock, flags);
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}
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static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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struct byt_gpio *vg = to_byt_gpio(chip);
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void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
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unsigned long flags;
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u32 value;
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spin_lock_irqsave(&vg->lock, flags);
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value = readl(reg) | BYT_DIR_MASK;
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value &= ~BYT_INPUT_EN; /* active low */
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writel(value, reg);
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spin_unlock_irqrestore(&vg->lock, flags);
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return 0;
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}
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static int byt_gpio_direction_output(struct gpio_chip *chip,
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unsigned gpio, int value)
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{
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struct byt_gpio *vg = to_byt_gpio(chip);
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void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG);
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unsigned long flags;
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u32 reg_val;
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spin_lock_irqsave(&vg->lock, flags);
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reg_val = readl(reg) | BYT_DIR_MASK;
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reg_val &= ~BYT_OUTPUT_EN;
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if (value)
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writel(reg_val | BYT_LEVEL, reg);
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else
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writel(reg_val & ~BYT_LEVEL, reg);
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spin_unlock_irqrestore(&vg->lock, flags);
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return 0;
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}
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static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
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{
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struct byt_gpio *vg = to_byt_gpio(chip);
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int i;
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unsigned long flags;
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u32 conf0, val, offs;
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spin_lock_irqsave(&vg->lock, flags);
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for (i = 0; i < vg->chip.ngpio; i++) {
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const char *label;
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offs = vg->range->pins[i] * 16;
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conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG);
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val = readl(vg->reg_base + offs + BYT_VAL_REG);
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label = gpiochip_is_requested(chip, i);
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if (!label)
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label = "Unrequested";
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seq_printf(s,
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" gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s\n",
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i,
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label,
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val & BYT_INPUT_EN ? " " : "in",
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val & BYT_OUTPUT_EN ? " " : "out",
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val & BYT_LEVEL ? "hi" : "lo",
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vg->range->pins[i], offs,
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conf0 & 0x7,
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conf0 & BYT_TRIG_NEG ? " fall" : "",
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conf0 & BYT_TRIG_POS ? " rise" : "",
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conf0 & BYT_TRIG_LVL ? " level" : "");
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}
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spin_unlock_irqrestore(&vg->lock, flags);
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}
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static int byt_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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struct byt_gpio *vg = to_byt_gpio(chip);
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return irq_create_mapping(vg->domain, offset);
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}
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static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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struct irq_data *data = irq_desc_get_irq_data(desc);
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struct byt_gpio *vg = irq_data_get_irq_handler_data(data);
|
|
struct irq_chip *chip = irq_data_get_irq_chip(data);
|
|
u32 base, pin, mask;
|
|
void __iomem *reg;
|
|
u32 pending;
|
|
unsigned virq;
|
|
int looplimit = 0;
|
|
|
|
/* check from GPIO controller which pin triggered the interrupt */
|
|
for (base = 0; base < vg->chip.ngpio; base += 32) {
|
|
|
|
reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
|
|
|
|
while ((pending = readl(reg))) {
|
|
pin = __ffs(pending);
|
|
mask = BIT(pin);
|
|
/* Clear before handling so we can't lose an edge */
|
|
writel(mask, reg);
|
|
|
|
virq = irq_find_mapping(vg->domain, base + pin);
|
|
generic_handle_irq(virq);
|
|
|
|
/* In case bios or user sets triggering incorretly a pin
|
|
* might remain in "interrupt triggered" state.
|
|
*/
|
|
if (looplimit++ > 32) {
|
|
dev_err(&vg->pdev->dev,
|
|
"Gpio %d interrupt flood, disabling\n",
|
|
base + pin);
|
|
|
|
reg = byt_gpio_reg(&vg->chip, base + pin,
|
|
BYT_CONF0_REG);
|
|
mask = readl(reg);
|
|
mask &= ~(BYT_TRIG_NEG | BYT_TRIG_POS |
|
|
BYT_TRIG_LVL);
|
|
writel(mask, reg);
|
|
mask = readl(reg); /* flush */
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
chip->irq_eoi(data);
|
|
}
|
|
|
|
static void byt_irq_unmask(struct irq_data *d)
|
|
{
|
|
}
|
|
|
|
static void byt_irq_mask(struct irq_data *d)
|
|
{
|
|
}
|
|
|
|
static int byt_irq_reqres(struct irq_data *d)
|
|
{
|
|
struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
|
|
|
|
if (gpio_lock_as_irq(&vg->chip, irqd_to_hwirq(d))) {
|
|
dev_err(vg->chip.dev,
|
|
"unable to lock HW IRQ %lu for IRQ\n",
|
|
irqd_to_hwirq(d));
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void byt_irq_relres(struct irq_data *d)
|
|
{
|
|
struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
|
|
|
|
gpio_unlock_as_irq(&vg->chip, irqd_to_hwirq(d));
|
|
}
|
|
|
|
static struct irq_chip byt_irqchip = {
|
|
.name = "BYT-GPIO",
|
|
.irq_mask = byt_irq_mask,
|
|
.irq_unmask = byt_irq_unmask,
|
|
.irq_set_type = byt_irq_type,
|
|
.irq_request_resources = byt_irq_reqres,
|
|
.irq_release_resources = byt_irq_relres,
|
|
};
|
|
|
|
static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
|
|
{
|
|
void __iomem *reg;
|
|
u32 base, value;
|
|
|
|
/* clear interrupt status trigger registers */
|
|
for (base = 0; base < vg->chip.ngpio; base += 32) {
|
|
reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
|
|
writel(0xffffffff, reg);
|
|
/* make sure trigger bits are cleared, if not then a pin
|
|
might be misconfigured in bios */
|
|
value = readl(reg);
|
|
if (value)
|
|
dev_err(&vg->pdev->dev,
|
|
"GPIO interrupt error, pins misconfigured\n");
|
|
}
|
|
}
|
|
|
|
static int byt_gpio_irq_map(struct irq_domain *d, unsigned int virq,
|
|
irq_hw_number_t hw)
|
|
{
|
|
struct byt_gpio *vg = d->host_data;
|
|
|
|
irq_set_chip_and_handler_name(virq, &byt_irqchip, handle_simple_irq,
|
|
"demux");
|
|
irq_set_chip_data(virq, vg);
|
|
irq_set_irq_type(virq, IRQ_TYPE_NONE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct irq_domain_ops byt_gpio_irq_ops = {
|
|
.map = byt_gpio_irq_map,
|
|
};
|
|
|
|
static int byt_gpio_probe(struct platform_device *pdev)
|
|
{
|
|
struct byt_gpio *vg;
|
|
struct gpio_chip *gc;
|
|
struct resource *mem_rc, *irq_rc;
|
|
struct device *dev = &pdev->dev;
|
|
struct acpi_device *acpi_dev;
|
|
struct pinctrl_gpio_range *range;
|
|
acpi_handle handle = ACPI_HANDLE(dev);
|
|
unsigned hwirq;
|
|
int ret;
|
|
|
|
if (acpi_bus_get_device(handle, &acpi_dev))
|
|
return -ENODEV;
|
|
|
|
vg = devm_kzalloc(dev, sizeof(struct byt_gpio), GFP_KERNEL);
|
|
if (!vg) {
|
|
dev_err(&pdev->dev, "can't allocate byt_gpio chip data\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
for (range = byt_ranges; range->name; range++) {
|
|
if (!strcmp(acpi_dev->pnp.unique_id, range->name)) {
|
|
vg->chip.ngpio = range->npins;
|
|
vg->range = range;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!vg->chip.ngpio || !vg->range)
|
|
return -ENODEV;
|
|
|
|
vg->pdev = pdev;
|
|
platform_set_drvdata(pdev, vg);
|
|
|
|
mem_rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
vg->reg_base = devm_ioremap_resource(dev, mem_rc);
|
|
if (IS_ERR(vg->reg_base))
|
|
return PTR_ERR(vg->reg_base);
|
|
|
|
spin_lock_init(&vg->lock);
|
|
|
|
gc = &vg->chip;
|
|
gc->label = dev_name(&pdev->dev);
|
|
gc->owner = THIS_MODULE;
|
|
gc->request = byt_gpio_request;
|
|
gc->free = byt_gpio_free;
|
|
gc->direction_input = byt_gpio_direction_input;
|
|
gc->direction_output = byt_gpio_direction_output;
|
|
gc->get = byt_gpio_get;
|
|
gc->set = byt_gpio_set;
|
|
gc->dbg_show = byt_gpio_dbg_show;
|
|
gc->base = -1;
|
|
gc->can_sleep = false;
|
|
gc->dev = dev;
|
|
|
|
ret = gpiochip_add(gc);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed adding byt-gpio chip\n");
|
|
return ret;
|
|
}
|
|
|
|
/* set up interrupts */
|
|
irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
|
if (irq_rc && irq_rc->start) {
|
|
hwirq = irq_rc->start;
|
|
gc->to_irq = byt_gpio_to_irq;
|
|
|
|
vg->domain = irq_domain_add_linear(NULL, gc->ngpio,
|
|
&byt_gpio_irq_ops, vg);
|
|
if (!vg->domain)
|
|
return -ENXIO;
|
|
|
|
byt_gpio_irq_init_hw(vg);
|
|
|
|
irq_set_handler_data(hwirq, vg);
|
|
irq_set_chained_handler(hwirq, byt_gpio_irq_handler);
|
|
}
|
|
|
|
pm_runtime_enable(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int byt_gpio_runtime_suspend(struct device *dev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int byt_gpio_runtime_resume(struct device *dev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops byt_gpio_pm_ops = {
|
|
.runtime_suspend = byt_gpio_runtime_suspend,
|
|
.runtime_resume = byt_gpio_runtime_resume,
|
|
};
|
|
|
|
static const struct acpi_device_id byt_gpio_acpi_match[] = {
|
|
{ "INT33B2", 0 },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
|
|
|
|
static int byt_gpio_remove(struct platform_device *pdev)
|
|
{
|
|
struct byt_gpio *vg = platform_get_drvdata(pdev);
|
|
int err;
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
err = gpiochip_remove(&vg->chip);
|
|
if (err)
|
|
dev_warn(&pdev->dev, "failed to remove gpio_chip.\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver byt_gpio_driver = {
|
|
.probe = byt_gpio_probe,
|
|
.remove = byt_gpio_remove,
|
|
.driver = {
|
|
.name = "byt_gpio",
|
|
.owner = THIS_MODULE,
|
|
.pm = &byt_gpio_pm_ops,
|
|
.acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
|
|
},
|
|
};
|
|
|
|
static int __init byt_gpio_init(void)
|
|
{
|
|
return platform_driver_register(&byt_gpio_driver);
|
|
}
|
|
|
|
subsys_initcall(byt_gpio_init);
|