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![Lyude](/assets/img/avatar_default.png)
When this code was written, we didn't retry DP aux transactions on any error, which required retrying important transactions like this in individual drivers. Since that's no longer the case, retrying here is not necessary. As well, we retry any aux transaction on any error 32 times. 7 * 32 = 224, which means this loop causes us to retry grabbing the dpcd 224 times. This is definitely far more then we actually need to do. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Lyude <cpaul@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
863 lines
24 KiB
C
863 lines
24 KiB
C
/*
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* Copyright 2007-8 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include <drm/drmP.h>
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#include <drm/radeon_drm.h>
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#include "radeon.h"
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#include "atom.h"
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#include "atom-bits.h"
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#include <drm/drm_dp_helper.h>
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/* move these to drm_dp_helper.c/h */
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#define DP_LINK_CONFIGURATION_SIZE 9
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#define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
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static char *voltage_names[] = {
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"0.4V", "0.6V", "0.8V", "1.2V"
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};
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static char *pre_emph_names[] = {
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"0dB", "3.5dB", "6dB", "9.5dB"
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};
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/***** radeon AUX functions *****/
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/* Atom needs data in little endian format
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* so swap as appropriate when copying data to
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* or from atom. Note that atom operates on
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* dw units.
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*/
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void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
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{
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#ifdef __BIG_ENDIAN
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u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
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u32 *dst32, *src32;
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int i;
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memcpy(src_tmp, src, num_bytes);
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src32 = (u32 *)src_tmp;
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dst32 = (u32 *)dst_tmp;
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if (to_le) {
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for (i = 0; i < ((num_bytes + 3) / 4); i++)
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dst32[i] = cpu_to_le32(src32[i]);
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memcpy(dst, dst_tmp, num_bytes);
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} else {
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u8 dws = num_bytes & ~3;
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for (i = 0; i < ((num_bytes + 3) / 4); i++)
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dst32[i] = le32_to_cpu(src32[i]);
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memcpy(dst, dst_tmp, dws);
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if (num_bytes % 4) {
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for (i = 0; i < (num_bytes % 4); i++)
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dst[dws+i] = dst_tmp[dws+i];
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}
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}
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#else
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memcpy(dst, src, num_bytes);
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#endif
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}
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union aux_channel_transaction {
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PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
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PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
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};
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static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
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u8 *send, int send_bytes,
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u8 *recv, int recv_size,
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u8 delay, u8 *ack)
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{
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struct drm_device *dev = chan->dev;
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struct radeon_device *rdev = dev->dev_private;
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union aux_channel_transaction args;
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int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
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unsigned char *base;
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int recv_bytes;
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int r = 0;
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memset(&args, 0, sizeof(args));
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mutex_lock(&chan->mutex);
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mutex_lock(&rdev->mode_info.atom_context->scratch_mutex);
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base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
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radeon_atom_copy_swap(base, send, send_bytes, true);
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args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
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args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4));
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args.v1.ucDataOutLen = 0;
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args.v1.ucChannelID = chan->rec.i2c_id;
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args.v1.ucDelay = delay / 10;
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if (ASIC_IS_DCE4(rdev))
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args.v2.ucHPD_ID = chan->rec.hpd;
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atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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*ack = args.v1.ucReplyStatus;
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/* timeout */
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if (args.v1.ucReplyStatus == 1) {
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DRM_DEBUG_KMS("dp_aux_ch timeout\n");
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r = -ETIMEDOUT;
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goto done;
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}
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/* flags not zero */
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if (args.v1.ucReplyStatus == 2) {
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DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
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r = -EIO;
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goto done;
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}
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/* error */
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if (args.v1.ucReplyStatus == 3) {
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DRM_DEBUG_KMS("dp_aux_ch error\n");
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r = -EIO;
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goto done;
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}
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recv_bytes = args.v1.ucDataOutLen;
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if (recv_bytes > recv_size)
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recv_bytes = recv_size;
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if (recv && recv_size)
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radeon_atom_copy_swap(recv, base + 16, recv_bytes, false);
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r = recv_bytes;
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done:
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mutex_unlock(&rdev->mode_info.atom_context->scratch_mutex);
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mutex_unlock(&chan->mutex);
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return r;
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}
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#define BARE_ADDRESS_SIZE 3
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#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
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static ssize_t
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radeon_dp_aux_transfer_atom(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
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{
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struct radeon_i2c_chan *chan =
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container_of(aux, struct radeon_i2c_chan, aux);
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int ret;
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u8 tx_buf[20];
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size_t tx_size;
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u8 ack, delay = 0;
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if (WARN_ON(msg->size > 16))
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return -E2BIG;
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tx_buf[0] = msg->address & 0xff;
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tx_buf[1] = (msg->address >> 8) & 0xff;
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tx_buf[2] = (msg->request << 4) |
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((msg->address >> 16) & 0xf);
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tx_buf[3] = msg->size ? (msg->size - 1) : 0;
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switch (msg->request & ~DP_AUX_I2C_MOT) {
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case DP_AUX_NATIVE_WRITE:
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case DP_AUX_I2C_WRITE:
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case DP_AUX_I2C_WRITE_STATUS_UPDATE:
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/* The atom implementation only supports writes with a max payload of
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* 12 bytes since it uses 4 bits for the total count (header + payload)
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* in the parameter space. The atom interface supports 16 byte
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* payloads for reads. The hw itself supports up to 16 bytes of payload.
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*/
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if (WARN_ON_ONCE(msg->size > 12))
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return -E2BIG;
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/* tx_size needs to be 4 even for bare address packets since the atom
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* table needs the info in tx_buf[3].
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*/
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tx_size = HEADER_SIZE + msg->size;
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if (msg->size == 0)
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tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
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else
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tx_buf[3] |= tx_size << 4;
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memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
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ret = radeon_process_aux_ch(chan,
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tx_buf, tx_size, NULL, 0, delay, &ack);
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if (ret >= 0)
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/* Return payload size. */
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ret = msg->size;
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break;
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case DP_AUX_NATIVE_READ:
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case DP_AUX_I2C_READ:
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/* tx_size needs to be 4 even for bare address packets since the atom
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* table needs the info in tx_buf[3].
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*/
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tx_size = HEADER_SIZE;
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if (msg->size == 0)
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tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
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else
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tx_buf[3] |= tx_size << 4;
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ret = radeon_process_aux_ch(chan,
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tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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if (ret >= 0)
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msg->reply = ack >> 4;
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return ret;
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}
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void radeon_dp_aux_init(struct radeon_connector *radeon_connector)
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{
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struct drm_device *dev = radeon_connector->base.dev;
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struct radeon_device *rdev = dev->dev_private;
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int ret;
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radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd;
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radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev;
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if (ASIC_IS_DCE5(rdev)) {
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if (radeon_auxch)
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radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_native;
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else
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radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom;
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} else {
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radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom;
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}
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ret = drm_dp_aux_register(&radeon_connector->ddc_bus->aux);
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if (!ret)
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radeon_connector->ddc_bus->has_aux = true;
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WARN(ret, "drm_dp_aux_register() failed with error %d\n", ret);
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}
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/***** general DP utility functions *****/
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#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3
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#define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3
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static void dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count,
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u8 train_set[4])
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{
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u8 v = 0;
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u8 p = 0;
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int lane;
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for (lane = 0; lane < lane_count; lane++) {
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u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
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u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
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DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
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lane,
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voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
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pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
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if (this_v > v)
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v = this_v;
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if (this_p > p)
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p = this_p;
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}
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if (v >= DP_VOLTAGE_MAX)
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v |= DP_TRAIN_MAX_SWING_REACHED;
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if (p >= DP_PRE_EMPHASIS_MAX)
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p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
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DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
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voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
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pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
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for (lane = 0; lane < 4; lane++)
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train_set[lane] = v | p;
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}
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/* convert bits per color to bits per pixel */
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/* get bpc from the EDID */
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static int convert_bpc_to_bpp(int bpc)
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{
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if (bpc == 0)
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return 24;
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else
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return bpc * 3;
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}
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/***** radeon specific DP functions *****/
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int radeon_dp_get_dp_link_config(struct drm_connector *connector,
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const u8 dpcd[DP_DPCD_SIZE],
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unsigned pix_clock,
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unsigned *dp_lanes, unsigned *dp_rate)
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{
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int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
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static const unsigned link_rates[3] = { 162000, 270000, 540000 };
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unsigned max_link_rate = drm_dp_max_link_rate(dpcd);
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unsigned max_lane_num = drm_dp_max_lane_count(dpcd);
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unsigned lane_num, i, max_pix_clock;
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if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
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ENCODER_OBJECT_ID_NUTMEG) {
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for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
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max_pix_clock = (lane_num * 270000 * 8) / bpp;
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if (max_pix_clock >= pix_clock) {
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*dp_lanes = lane_num;
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*dp_rate = 270000;
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return 0;
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}
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}
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} else {
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for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {
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for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
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max_pix_clock = (lane_num * link_rates[i] * 8) / bpp;
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if (max_pix_clock >= pix_clock) {
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*dp_lanes = lane_num;
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*dp_rate = link_rates[i];
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return 0;
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}
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}
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}
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}
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return -EINVAL;
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}
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static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
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int action, int dp_clock,
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u8 ucconfig, u8 lane_num)
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{
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DP_ENCODER_SERVICE_PARAMETERS args;
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int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
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memset(&args, 0, sizeof(args));
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args.ucLinkClock = dp_clock / 10;
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args.ucConfig = ucconfig;
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args.ucAction = action;
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args.ucLaneNum = lane_num;
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args.ucStatus = 0;
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atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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return args.ucStatus;
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}
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u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
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{
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struct drm_device *dev = radeon_connector->base.dev;
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struct radeon_device *rdev = dev->dev_private;
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return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
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radeon_connector->ddc_bus->rec.i2c_id, 0);
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}
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static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
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{
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struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
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u8 buf[3];
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if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
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return;
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if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
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DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
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buf[0], buf[1], buf[2]);
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if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
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DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
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buf[0], buf[1], buf[2]);
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}
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bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
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{
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struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
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u8 msg[DP_DPCD_SIZE];
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int ret;
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ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
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DP_DPCD_SIZE);
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if (ret == DP_DPCD_SIZE) {
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memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
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DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
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dig_connector->dpcd);
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radeon_dp_probe_oui(radeon_connector);
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return true;
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}
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dig_connector->dpcd[0] = 0;
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return false;
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}
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int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
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struct drm_connector *connector)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_connector *radeon_connector = to_radeon_connector(connector);
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struct radeon_connector_atom_dig *dig_connector;
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int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
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u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
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u8 tmp;
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if (!ASIC_IS_DCE4(rdev))
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return panel_mode;
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if (!radeon_connector->con_priv)
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return panel_mode;
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dig_connector = radeon_connector->con_priv;
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if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
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/* DP bridge chips */
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if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
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DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
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if (tmp & 1)
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panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
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else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
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(dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
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panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
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else
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panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
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}
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} else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
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/* eDP */
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if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
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DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
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if (tmp & 1)
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panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
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}
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}
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return panel_mode;
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}
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|
|
void radeon_dp_set_link_config(struct drm_connector *connector,
|
|
const struct drm_display_mode *mode)
|
|
{
|
|
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
|
|
struct radeon_connector_atom_dig *dig_connector;
|
|
int ret;
|
|
|
|
if (!radeon_connector->con_priv)
|
|
return;
|
|
dig_connector = radeon_connector->con_priv;
|
|
|
|
if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
|
|
(dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
|
|
ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd,
|
|
mode->clock,
|
|
&dig_connector->dp_lane_count,
|
|
&dig_connector->dp_clock);
|
|
if (ret) {
|
|
dig_connector->dp_clock = 0;
|
|
dig_connector->dp_lane_count = 0;
|
|
}
|
|
}
|
|
}
|
|
|
|
int radeon_dp_mode_valid_helper(struct drm_connector *connector,
|
|
struct drm_display_mode *mode)
|
|
{
|
|
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
|
|
struct radeon_connector_atom_dig *dig_connector;
|
|
unsigned dp_clock, dp_lanes;
|
|
int ret;
|
|
|
|
if ((mode->clock > 340000) &&
|
|
(!radeon_connector_is_dp12_capable(connector)))
|
|
return MODE_CLOCK_HIGH;
|
|
|
|
if (!radeon_connector->con_priv)
|
|
return MODE_CLOCK_HIGH;
|
|
dig_connector = radeon_connector->con_priv;
|
|
|
|
ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd,
|
|
mode->clock,
|
|
&dp_lanes,
|
|
&dp_clock);
|
|
if (ret)
|
|
return MODE_CLOCK_HIGH;
|
|
|
|
if ((dp_clock == 540000) &&
|
|
(!radeon_connector_is_dp12_capable(connector)))
|
|
return MODE_CLOCK_HIGH;
|
|
|
|
return MODE_OK;
|
|
}
|
|
|
|
bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
|
|
{
|
|
u8 link_status[DP_LINK_STATUS_SIZE];
|
|
struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
|
|
|
|
if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux, link_status)
|
|
<= 0)
|
|
return false;
|
|
if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
|
|
return false;
|
|
return true;
|
|
}
|
|
|
|
void radeon_dp_set_rx_power_state(struct drm_connector *connector,
|
|
u8 power_state)
|
|
{
|
|
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
|
|
struct radeon_connector_atom_dig *dig_connector;
|
|
|
|
if (!radeon_connector->con_priv)
|
|
return;
|
|
|
|
dig_connector = radeon_connector->con_priv;
|
|
|
|
/* power up/down the sink */
|
|
if (dig_connector->dpcd[0] >= 0x11) {
|
|
drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux,
|
|
DP_SET_POWER, power_state);
|
|
usleep_range(1000, 2000);
|
|
}
|
|
}
|
|
|
|
|
|
struct radeon_dp_link_train_info {
|
|
struct radeon_device *rdev;
|
|
struct drm_encoder *encoder;
|
|
struct drm_connector *connector;
|
|
int enc_id;
|
|
int dp_clock;
|
|
int dp_lane_count;
|
|
bool tp3_supported;
|
|
u8 dpcd[DP_RECEIVER_CAP_SIZE];
|
|
u8 train_set[4];
|
|
u8 link_status[DP_LINK_STATUS_SIZE];
|
|
u8 tries;
|
|
bool use_dpencoder;
|
|
struct drm_dp_aux *aux;
|
|
};
|
|
|
|
static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
|
|
{
|
|
/* set the initial vs/emph on the source */
|
|
atombios_dig_transmitter_setup(dp_info->encoder,
|
|
ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
|
|
0, dp_info->train_set[0]); /* sets all lanes at once */
|
|
|
|
/* set the vs/emph on the sink */
|
|
drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
|
|
dp_info->train_set, dp_info->dp_lane_count);
|
|
}
|
|
|
|
static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
|
|
{
|
|
int rtp = 0;
|
|
|
|
/* set training pattern on the source */
|
|
if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
|
|
switch (tp) {
|
|
case DP_TRAINING_PATTERN_1:
|
|
rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
|
|
break;
|
|
case DP_TRAINING_PATTERN_2:
|
|
rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
|
|
break;
|
|
case DP_TRAINING_PATTERN_3:
|
|
rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
|
|
break;
|
|
}
|
|
atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
|
|
} else {
|
|
switch (tp) {
|
|
case DP_TRAINING_PATTERN_1:
|
|
rtp = 0;
|
|
break;
|
|
case DP_TRAINING_PATTERN_2:
|
|
rtp = 1;
|
|
break;
|
|
}
|
|
radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
|
|
dp_info->dp_clock, dp_info->enc_id, rtp);
|
|
}
|
|
|
|
/* enable training pattern on the sink */
|
|
drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
|
|
}
|
|
|
|
static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
|
|
{
|
|
struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
|
|
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
|
|
u8 tmp;
|
|
|
|
/* power up the sink */
|
|
radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
|
|
|
|
/* possibly enable downspread on the sink */
|
|
if (dp_info->dpcd[3] & 0x1)
|
|
drm_dp_dpcd_writeb(dp_info->aux,
|
|
DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
|
|
else
|
|
drm_dp_dpcd_writeb(dp_info->aux,
|
|
DP_DOWNSPREAD_CTRL, 0);
|
|
|
|
if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)
|
|
drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
|
|
|
|
/* set the lane count on the sink */
|
|
tmp = dp_info->dp_lane_count;
|
|
if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
|
|
tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
|
|
drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
|
|
|
|
/* set the link rate on the sink */
|
|
tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
|
|
drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
|
|
|
|
/* start training on the source */
|
|
if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
|
|
atombios_dig_encoder_setup(dp_info->encoder,
|
|
ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
|
|
else
|
|
radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
|
|
dp_info->dp_clock, dp_info->enc_id, 0);
|
|
|
|
/* disable the training pattern on the sink */
|
|
drm_dp_dpcd_writeb(dp_info->aux,
|
|
DP_TRAINING_PATTERN_SET,
|
|
DP_TRAINING_PATTERN_DISABLE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
|
|
{
|
|
udelay(400);
|
|
|
|
/* disable the training pattern on the sink */
|
|
drm_dp_dpcd_writeb(dp_info->aux,
|
|
DP_TRAINING_PATTERN_SET,
|
|
DP_TRAINING_PATTERN_DISABLE);
|
|
|
|
/* disable the training pattern on the source */
|
|
if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
|
|
atombios_dig_encoder_setup(dp_info->encoder,
|
|
ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
|
|
else
|
|
radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
|
|
dp_info->dp_clock, dp_info->enc_id, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
|
|
{
|
|
bool clock_recovery;
|
|
u8 voltage;
|
|
int i;
|
|
|
|
radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
|
|
memset(dp_info->train_set, 0, 4);
|
|
radeon_dp_update_vs_emph(dp_info);
|
|
|
|
udelay(400);
|
|
|
|
/* clock recovery loop */
|
|
clock_recovery = false;
|
|
dp_info->tries = 0;
|
|
voltage = 0xff;
|
|
while (1) {
|
|
drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
|
|
|
|
if (drm_dp_dpcd_read_link_status(dp_info->aux,
|
|
dp_info->link_status) <= 0) {
|
|
DRM_ERROR("displayport link status failed\n");
|
|
break;
|
|
}
|
|
|
|
if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
|
|
clock_recovery = true;
|
|
break;
|
|
}
|
|
|
|
for (i = 0; i < dp_info->dp_lane_count; i++) {
|
|
if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
|
|
break;
|
|
}
|
|
if (i == dp_info->dp_lane_count) {
|
|
DRM_ERROR("clock recovery reached max voltage\n");
|
|
break;
|
|
}
|
|
|
|
if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
|
|
++dp_info->tries;
|
|
if (dp_info->tries == 5) {
|
|
DRM_ERROR("clock recovery tried 5 times\n");
|
|
break;
|
|
}
|
|
} else
|
|
dp_info->tries = 0;
|
|
|
|
voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
|
|
|
|
/* Compute new train_set as requested by sink */
|
|
dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
|
|
|
|
radeon_dp_update_vs_emph(dp_info);
|
|
}
|
|
if (!clock_recovery) {
|
|
DRM_ERROR("clock recovery failed\n");
|
|
return -1;
|
|
} else {
|
|
DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
|
|
dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
|
|
(dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
|
|
DP_TRAIN_PRE_EMPHASIS_SHIFT);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
|
|
{
|
|
bool channel_eq;
|
|
|
|
if (dp_info->tp3_supported)
|
|
radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
|
|
else
|
|
radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
|
|
|
|
/* channel equalization loop */
|
|
dp_info->tries = 0;
|
|
channel_eq = false;
|
|
while (1) {
|
|
drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
|
|
|
|
if (drm_dp_dpcd_read_link_status(dp_info->aux,
|
|
dp_info->link_status) <= 0) {
|
|
DRM_ERROR("displayport link status failed\n");
|
|
break;
|
|
}
|
|
|
|
if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
|
|
channel_eq = true;
|
|
break;
|
|
}
|
|
|
|
/* Try 5 times */
|
|
if (dp_info->tries > 5) {
|
|
DRM_ERROR("channel eq failed: 5 tries\n");
|
|
break;
|
|
}
|
|
|
|
/* Compute new train_set as requested by sink */
|
|
dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
|
|
|
|
radeon_dp_update_vs_emph(dp_info);
|
|
dp_info->tries++;
|
|
}
|
|
|
|
if (!channel_eq) {
|
|
DRM_ERROR("channel eq failed\n");
|
|
return -1;
|
|
} else {
|
|
DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
|
|
dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
|
|
(dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
|
|
>> DP_TRAIN_PRE_EMPHASIS_SHIFT);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
void radeon_dp_link_train(struct drm_encoder *encoder,
|
|
struct drm_connector *connector)
|
|
{
|
|
struct drm_device *dev = encoder->dev;
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
|
|
struct radeon_encoder_atom_dig *dig;
|
|
struct radeon_connector *radeon_connector;
|
|
struct radeon_connector_atom_dig *dig_connector;
|
|
struct radeon_dp_link_train_info dp_info;
|
|
int index;
|
|
u8 tmp, frev, crev;
|
|
|
|
if (!radeon_encoder->enc_priv)
|
|
return;
|
|
dig = radeon_encoder->enc_priv;
|
|
|
|
radeon_connector = to_radeon_connector(connector);
|
|
if (!radeon_connector->con_priv)
|
|
return;
|
|
dig_connector = radeon_connector->con_priv;
|
|
|
|
if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
|
|
(dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
|
|
return;
|
|
|
|
/* DPEncoderService newer than 1.1 can't program properly the
|
|
* training pattern. When facing such version use the
|
|
* DIGXEncoderControl (X== 1 | 2)
|
|
*/
|
|
dp_info.use_dpencoder = true;
|
|
index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
|
|
if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
|
|
if (crev > 1) {
|
|
dp_info.use_dpencoder = false;
|
|
}
|
|
}
|
|
|
|
dp_info.enc_id = 0;
|
|
if (dig->dig_encoder)
|
|
dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
|
|
else
|
|
dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
|
|
if (dig->linkb)
|
|
dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
|
|
else
|
|
dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
|
|
|
|
if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
|
|
== 1) {
|
|
if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
|
|
dp_info.tp3_supported = true;
|
|
else
|
|
dp_info.tp3_supported = false;
|
|
} else {
|
|
dp_info.tp3_supported = false;
|
|
}
|
|
|
|
memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
|
|
dp_info.rdev = rdev;
|
|
dp_info.encoder = encoder;
|
|
dp_info.connector = connector;
|
|
dp_info.dp_lane_count = dig_connector->dp_lane_count;
|
|
dp_info.dp_clock = dig_connector->dp_clock;
|
|
dp_info.aux = &radeon_connector->ddc_bus->aux;
|
|
|
|
if (radeon_dp_link_train_init(&dp_info))
|
|
goto done;
|
|
if (radeon_dp_link_train_cr(&dp_info))
|
|
goto done;
|
|
if (radeon_dp_link_train_ce(&dp_info))
|
|
goto done;
|
|
done:
|
|
if (radeon_dp_link_train_finish(&dp_info))
|
|
return;
|
|
}
|