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![David Howells](/assets/img/avatar_default.png)
Convert #include "..." to #include <path/...> in drivers/gpu/. Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Dave Airlie <airlied@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Acked-by: Dave Jones <davej@redhat.com>
912 lines
26 KiB
C
912 lines
26 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include <drm/drmP.h>
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#include <drm/radeon_drm.h>
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#include "radeon_reg.h"
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#include "radeon.h"
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#include "atom.h"
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/* 10 khz */
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uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev)
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{
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struct radeon_pll *spll = &rdev->clock.spll;
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uint32_t fb_div, ref_div, post_div, sclk;
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fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
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fb_div = (fb_div >> RADEON_SPLL_FB_DIV_SHIFT) & RADEON_SPLL_FB_DIV_MASK;
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fb_div <<= 1;
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fb_div *= spll->reference_freq;
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ref_div =
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RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
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if (ref_div == 0)
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return 0;
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sclk = fb_div / ref_div;
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post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK;
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if (post_div == 2)
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sclk >>= 1;
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else if (post_div == 3)
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sclk >>= 2;
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else if (post_div == 4)
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sclk >>= 3;
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return sclk;
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}
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/* 10 khz */
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uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
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{
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struct radeon_pll *mpll = &rdev->clock.mpll;
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uint32_t fb_div, ref_div, post_div, mclk;
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fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
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fb_div = (fb_div >> RADEON_MPLL_FB_DIV_SHIFT) & RADEON_MPLL_FB_DIV_MASK;
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fb_div <<= 1;
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fb_div *= mpll->reference_freq;
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ref_div =
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RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
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if (ref_div == 0)
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return 0;
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mclk = fb_div / ref_div;
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post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7;
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if (post_div == 2)
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mclk >>= 1;
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else if (post_div == 3)
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mclk >>= 2;
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else if (post_div == 4)
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mclk >>= 3;
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return mclk;
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}
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#ifdef CONFIG_OF
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/*
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* Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
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* tree. Hopefully, ATI OF driver is kind enough to fill these
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*/
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static bool radeon_read_clocks_OF(struct drm_device *dev)
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{
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struct radeon_device *rdev = dev->dev_private;
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struct device_node *dp = rdev->pdev->dev.of_node;
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const u32 *val;
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struct radeon_pll *p1pll = &rdev->clock.p1pll;
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struct radeon_pll *p2pll = &rdev->clock.p2pll;
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struct radeon_pll *spll = &rdev->clock.spll;
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struct radeon_pll *mpll = &rdev->clock.mpll;
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if (dp == NULL)
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return false;
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val = of_get_property(dp, "ATY,RefCLK", NULL);
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if (!val || !*val) {
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printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
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return false;
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}
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p1pll->reference_freq = p2pll->reference_freq = (*val) / 10;
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p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
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if (p1pll->reference_div < 2)
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p1pll->reference_div = 12;
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p2pll->reference_div = p1pll->reference_div;
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/* These aren't in the device-tree */
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if (rdev->family >= CHIP_R420) {
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p1pll->pll_in_min = 100;
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p1pll->pll_in_max = 1350;
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p1pll->pll_out_min = 20000;
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p1pll->pll_out_max = 50000;
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p2pll->pll_in_min = 100;
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p2pll->pll_in_max = 1350;
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p2pll->pll_out_min = 20000;
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p2pll->pll_out_max = 50000;
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} else {
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p1pll->pll_in_min = 40;
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p1pll->pll_in_max = 500;
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p1pll->pll_out_min = 12500;
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p1pll->pll_out_max = 35000;
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p2pll->pll_in_min = 40;
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p2pll->pll_in_max = 500;
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p2pll->pll_out_min = 12500;
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p2pll->pll_out_max = 35000;
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}
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/* not sure what the max should be in all cases */
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rdev->clock.max_pixel_clock = 35000;
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spll->reference_freq = mpll->reference_freq = p1pll->reference_freq;
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spll->reference_div = mpll->reference_div =
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RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
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RADEON_M_SPLL_REF_DIV_MASK;
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val = of_get_property(dp, "ATY,SCLK", NULL);
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if (val && *val)
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rdev->clock.default_sclk = (*val) / 10;
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else
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rdev->clock.default_sclk =
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radeon_legacy_get_engine_clock(rdev);
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val = of_get_property(dp, "ATY,MCLK", NULL);
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if (val && *val)
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rdev->clock.default_mclk = (*val) / 10;
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else
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rdev->clock.default_mclk =
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radeon_legacy_get_memory_clock(rdev);
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DRM_INFO("Using device-tree clock info\n");
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return true;
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}
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#else
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static bool radeon_read_clocks_OF(struct drm_device *dev)
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{
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return false;
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}
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#endif /* CONFIG_OF */
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void radeon_get_clock_info(struct drm_device *dev)
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{
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_pll *p1pll = &rdev->clock.p1pll;
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struct radeon_pll *p2pll = &rdev->clock.p2pll;
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struct radeon_pll *dcpll = &rdev->clock.dcpll;
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struct radeon_pll *spll = &rdev->clock.spll;
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struct radeon_pll *mpll = &rdev->clock.mpll;
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int ret;
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if (rdev->is_atom_bios)
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ret = radeon_atom_get_clock_info(dev);
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else
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ret = radeon_combios_get_clock_info(dev);
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if (!ret)
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ret = radeon_read_clocks_OF(dev);
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if (ret) {
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if (p1pll->reference_div < 2) {
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if (!ASIC_IS_AVIVO(rdev)) {
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u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV);
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if (ASIC_IS_R300(rdev))
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p1pll->reference_div =
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(tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT;
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else
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p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK;
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if (p1pll->reference_div < 2)
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p1pll->reference_div = 12;
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} else
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p1pll->reference_div = 12;
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}
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if (p2pll->reference_div < 2)
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p2pll->reference_div = 12;
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if (rdev->family < CHIP_RS600) {
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if (spll->reference_div < 2)
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spll->reference_div =
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RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
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RADEON_M_SPLL_REF_DIV_MASK;
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}
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if (mpll->reference_div < 2)
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mpll->reference_div = spll->reference_div;
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} else {
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if (ASIC_IS_AVIVO(rdev)) {
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/* TODO FALLBACK */
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} else {
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DRM_INFO("Using generic clock info\n");
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/* may need to be per card */
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rdev->clock.max_pixel_clock = 35000;
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if (rdev->flags & RADEON_IS_IGP) {
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p1pll->reference_freq = 1432;
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p2pll->reference_freq = 1432;
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spll->reference_freq = 1432;
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mpll->reference_freq = 1432;
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} else {
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p1pll->reference_freq = 2700;
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p2pll->reference_freq = 2700;
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spll->reference_freq = 2700;
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mpll->reference_freq = 2700;
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}
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p1pll->reference_div =
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RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
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if (p1pll->reference_div < 2)
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p1pll->reference_div = 12;
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p2pll->reference_div = p1pll->reference_div;
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if (rdev->family >= CHIP_R420) {
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p1pll->pll_in_min = 100;
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p1pll->pll_in_max = 1350;
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p1pll->pll_out_min = 20000;
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p1pll->pll_out_max = 50000;
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p2pll->pll_in_min = 100;
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p2pll->pll_in_max = 1350;
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p2pll->pll_out_min = 20000;
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p2pll->pll_out_max = 50000;
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} else {
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p1pll->pll_in_min = 40;
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p1pll->pll_in_max = 500;
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p1pll->pll_out_min = 12500;
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p1pll->pll_out_max = 35000;
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p2pll->pll_in_min = 40;
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p2pll->pll_in_max = 500;
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p2pll->pll_out_min = 12500;
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p2pll->pll_out_max = 35000;
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}
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spll->reference_div =
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RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
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RADEON_M_SPLL_REF_DIV_MASK;
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mpll->reference_div = spll->reference_div;
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rdev->clock.default_sclk =
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radeon_legacy_get_engine_clock(rdev);
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rdev->clock.default_mclk =
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radeon_legacy_get_memory_clock(rdev);
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}
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}
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/* pixel clocks */
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if (ASIC_IS_AVIVO(rdev)) {
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p1pll->min_post_div = 2;
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p1pll->max_post_div = 0x7f;
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p1pll->min_frac_feedback_div = 0;
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p1pll->max_frac_feedback_div = 9;
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p2pll->min_post_div = 2;
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p2pll->max_post_div = 0x7f;
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p2pll->min_frac_feedback_div = 0;
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p2pll->max_frac_feedback_div = 9;
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} else {
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p1pll->min_post_div = 1;
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p1pll->max_post_div = 16;
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p1pll->min_frac_feedback_div = 0;
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p1pll->max_frac_feedback_div = 0;
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p2pll->min_post_div = 1;
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p2pll->max_post_div = 12;
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p2pll->min_frac_feedback_div = 0;
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p2pll->max_frac_feedback_div = 0;
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}
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/* dcpll is DCE4 only */
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dcpll->min_post_div = 2;
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dcpll->max_post_div = 0x7f;
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dcpll->min_frac_feedback_div = 0;
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dcpll->max_frac_feedback_div = 9;
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dcpll->min_ref_div = 2;
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dcpll->max_ref_div = 0x3ff;
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dcpll->min_feedback_div = 4;
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dcpll->max_feedback_div = 0xfff;
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dcpll->best_vco = 0;
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p1pll->min_ref_div = 2;
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p1pll->max_ref_div = 0x3ff;
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p1pll->min_feedback_div = 4;
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p1pll->max_feedback_div = 0x7ff;
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p1pll->best_vco = 0;
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p2pll->min_ref_div = 2;
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p2pll->max_ref_div = 0x3ff;
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p2pll->min_feedback_div = 4;
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p2pll->max_feedback_div = 0x7ff;
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p2pll->best_vco = 0;
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/* system clock */
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spll->min_post_div = 1;
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spll->max_post_div = 1;
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spll->min_ref_div = 2;
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spll->max_ref_div = 0xff;
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spll->min_feedback_div = 4;
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spll->max_feedback_div = 0xff;
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spll->best_vco = 0;
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/* memory clock */
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mpll->min_post_div = 1;
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mpll->max_post_div = 1;
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mpll->min_ref_div = 2;
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mpll->max_ref_div = 0xff;
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mpll->min_feedback_div = 4;
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mpll->max_feedback_div = 0xff;
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mpll->best_vco = 0;
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if (!rdev->clock.default_sclk)
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rdev->clock.default_sclk = radeon_get_engine_clock(rdev);
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if ((!rdev->clock.default_mclk) && rdev->asic->pm.get_memory_clock)
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rdev->clock.default_mclk = radeon_get_memory_clock(rdev);
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rdev->pm.current_sclk = rdev->clock.default_sclk;
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rdev->pm.current_mclk = rdev->clock.default_mclk;
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}
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/* 10 khz */
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static uint32_t calc_eng_mem_clock(struct radeon_device *rdev,
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uint32_t req_clock,
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int *fb_div, int *post_div)
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{
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struct radeon_pll *spll = &rdev->clock.spll;
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int ref_div = spll->reference_div;
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if (!ref_div)
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ref_div =
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RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
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RADEON_M_SPLL_REF_DIV_MASK;
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if (req_clock < 15000) {
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*post_div = 8;
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req_clock *= 8;
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} else if (req_clock < 30000) {
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*post_div = 4;
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req_clock *= 4;
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} else if (req_clock < 60000) {
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*post_div = 2;
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req_clock *= 2;
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} else
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*post_div = 1;
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req_clock *= ref_div;
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req_clock += spll->reference_freq;
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req_clock /= (2 * spll->reference_freq);
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*fb_div = req_clock & 0xff;
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req_clock = (req_clock & 0xffff) << 1;
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req_clock *= spll->reference_freq;
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req_clock /= ref_div;
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req_clock /= *post_div;
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return req_clock;
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}
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/* 10 khz */
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void radeon_legacy_set_engine_clock(struct radeon_device *rdev,
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uint32_t eng_clock)
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{
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uint32_t tmp;
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int fb_div, post_div;
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/* XXX: wait for idle */
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eng_clock = calc_eng_mem_clock(rdev, eng_clock, &fb_div, &post_div);
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tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
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tmp &= ~RADEON_DONT_USE_XTALIN;
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WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
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tmp = RREG32_PLL(RADEON_SCLK_CNTL);
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tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
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WREG32_PLL(RADEON_SCLK_CNTL, tmp);
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udelay(10);
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tmp = RREG32_PLL(RADEON_SPLL_CNTL);
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tmp |= RADEON_SPLL_SLEEP;
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WREG32_PLL(RADEON_SPLL_CNTL, tmp);
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udelay(2);
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tmp = RREG32_PLL(RADEON_SPLL_CNTL);
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tmp |= RADEON_SPLL_RESET;
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WREG32_PLL(RADEON_SPLL_CNTL, tmp);
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udelay(200);
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tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
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tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT);
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tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT;
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WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp);
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/* XXX: verify on different asics */
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tmp = RREG32_PLL(RADEON_SPLL_CNTL);
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tmp &= ~RADEON_SPLL_PVG_MASK;
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if ((eng_clock * post_div) >= 90000)
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tmp |= (0x7 << RADEON_SPLL_PVG_SHIFT);
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else
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tmp |= (0x4 << RADEON_SPLL_PVG_SHIFT);
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WREG32_PLL(RADEON_SPLL_CNTL, tmp);
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tmp = RREG32_PLL(RADEON_SPLL_CNTL);
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tmp &= ~RADEON_SPLL_SLEEP;
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WREG32_PLL(RADEON_SPLL_CNTL, tmp);
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udelay(2);
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tmp = RREG32_PLL(RADEON_SPLL_CNTL);
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tmp &= ~RADEON_SPLL_RESET;
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WREG32_PLL(RADEON_SPLL_CNTL, tmp);
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udelay(200);
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tmp = RREG32_PLL(RADEON_SCLK_CNTL);
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tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
|
|
switch (post_div) {
|
|
case 1:
|
|
default:
|
|
tmp |= 1;
|
|
break;
|
|
case 2:
|
|
tmp |= 2;
|
|
break;
|
|
case 4:
|
|
tmp |= 3;
|
|
break;
|
|
case 8:
|
|
tmp |= 4;
|
|
break;
|
|
}
|
|
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
|
|
|
|
udelay(20);
|
|
|
|
tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
|
|
tmp |= RADEON_DONT_USE_XTALIN;
|
|
WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
|
|
|
|
udelay(10);
|
|
}
|
|
|
|
void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
|
|
{
|
|
uint32_t tmp;
|
|
|
|
if (enable) {
|
|
if (rdev->flags & RADEON_SINGLE_CRTC) {
|
|
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
|
|
if ((RREG32(RADEON_CONFIG_CNTL) &
|
|
RADEON_CFG_ATI_REV_ID_MASK) >
|
|
RADEON_CFG_ATI_REV_A13) {
|
|
tmp &=
|
|
~(RADEON_SCLK_FORCE_CP |
|
|
RADEON_SCLK_FORCE_RB);
|
|
}
|
|
tmp &=
|
|
~(RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 |
|
|
RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_SE |
|
|
RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_RE |
|
|
RADEON_SCLK_FORCE_PB | RADEON_SCLK_FORCE_TAM |
|
|
RADEON_SCLK_FORCE_TDM);
|
|
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
|
|
} else if (ASIC_IS_R300(rdev)) {
|
|
if ((rdev->family == CHIP_RS400) ||
|
|
(rdev->family == CHIP_RS480)) {
|
|
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
|
|
tmp &=
|
|
~(RADEON_SCLK_FORCE_DISP2 |
|
|
RADEON_SCLK_FORCE_CP |
|
|
RADEON_SCLK_FORCE_HDP |
|
|
RADEON_SCLK_FORCE_DISP1 |
|
|
RADEON_SCLK_FORCE_TOP |
|
|
RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP
|
|
| RADEON_SCLK_FORCE_IDCT |
|
|
RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR
|
|
| R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX
|
|
| R300_SCLK_FORCE_US |
|
|
RADEON_SCLK_FORCE_TV_SCLK |
|
|
R300_SCLK_FORCE_SU |
|
|
RADEON_SCLK_FORCE_OV0);
|
|
tmp |= RADEON_DYN_STOP_LAT_MASK;
|
|
tmp |=
|
|
RADEON_SCLK_FORCE_TOP |
|
|
RADEON_SCLK_FORCE_VIP;
|
|
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
|
|
|
|
tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
|
|
tmp &= ~RADEON_SCLK_MORE_FORCEON;
|
|
tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
|
|
WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
|
|
|
|
tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
|
|
tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
|
|
RADEON_PIXCLK_DAC_ALWAYS_ONb);
|
|
WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
|
|
|
|
tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
|
|
tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
|
|
RADEON_PIX2CLK_DAC_ALWAYS_ONb |
|
|
RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
|
|
R300_DVOCLK_ALWAYS_ONb |
|
|
RADEON_PIXCLK_BLEND_ALWAYS_ONb |
|
|
RADEON_PIXCLK_GV_ALWAYS_ONb |
|
|
R300_PIXCLK_DVO_ALWAYS_ONb |
|
|
RADEON_PIXCLK_LVDS_ALWAYS_ONb |
|
|
RADEON_PIXCLK_TMDS_ALWAYS_ONb |
|
|
R300_PIXCLK_TRANS_ALWAYS_ONb |
|
|
R300_PIXCLK_TVO_ALWAYS_ONb |
|
|
R300_P2G2CLK_ALWAYS_ONb |
|
|
R300_P2G2CLK_DAC_ALWAYS_ONb);
|
|
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
|
|
} else if (rdev->family >= CHIP_RV350) {
|
|
tmp = RREG32_PLL(R300_SCLK_CNTL2);
|
|
tmp &= ~(R300_SCLK_FORCE_TCL |
|
|
R300_SCLK_FORCE_GA |
|
|
R300_SCLK_FORCE_CBA);
|
|
tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT |
|
|
R300_SCLK_GA_MAX_DYN_STOP_LAT |
|
|
R300_SCLK_CBA_MAX_DYN_STOP_LAT);
|
|
WREG32_PLL(R300_SCLK_CNTL2, tmp);
|
|
|
|
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
|
|
tmp &=
|
|
~(RADEON_SCLK_FORCE_DISP2 |
|
|
RADEON_SCLK_FORCE_CP |
|
|
RADEON_SCLK_FORCE_HDP |
|
|
RADEON_SCLK_FORCE_DISP1 |
|
|
RADEON_SCLK_FORCE_TOP |
|
|
RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP
|
|
| RADEON_SCLK_FORCE_IDCT |
|
|
RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR
|
|
| R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX
|
|
| R300_SCLK_FORCE_US |
|
|
RADEON_SCLK_FORCE_TV_SCLK |
|
|
R300_SCLK_FORCE_SU |
|
|
RADEON_SCLK_FORCE_OV0);
|
|
tmp |= RADEON_DYN_STOP_LAT_MASK;
|
|
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
|
|
|
|
tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
|
|
tmp &= ~RADEON_SCLK_MORE_FORCEON;
|
|
tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
|
|
WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
|
|
|
|
tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
|
|
tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
|
|
RADEON_PIXCLK_DAC_ALWAYS_ONb);
|
|
WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
|
|
|
|
tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
|
|
tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
|
|
RADEON_PIX2CLK_DAC_ALWAYS_ONb |
|
|
RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
|
|
R300_DVOCLK_ALWAYS_ONb |
|
|
RADEON_PIXCLK_BLEND_ALWAYS_ONb |
|
|
RADEON_PIXCLK_GV_ALWAYS_ONb |
|
|
R300_PIXCLK_DVO_ALWAYS_ONb |
|
|
RADEON_PIXCLK_LVDS_ALWAYS_ONb |
|
|
RADEON_PIXCLK_TMDS_ALWAYS_ONb |
|
|
R300_PIXCLK_TRANS_ALWAYS_ONb |
|
|
R300_PIXCLK_TVO_ALWAYS_ONb |
|
|
R300_P2G2CLK_ALWAYS_ONb |
|
|
R300_P2G2CLK_DAC_ALWAYS_ONb);
|
|
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
|
|
|
|
tmp = RREG32_PLL(RADEON_MCLK_MISC);
|
|
tmp |= (RADEON_MC_MCLK_DYN_ENABLE |
|
|
RADEON_IO_MCLK_DYN_ENABLE);
|
|
WREG32_PLL(RADEON_MCLK_MISC, tmp);
|
|
|
|
tmp = RREG32_PLL(RADEON_MCLK_CNTL);
|
|
tmp |= (RADEON_FORCEON_MCLKA |
|
|
RADEON_FORCEON_MCLKB);
|
|
|
|
tmp &= ~(RADEON_FORCEON_YCLKA |
|
|
RADEON_FORCEON_YCLKB |
|
|
RADEON_FORCEON_MC);
|
|
|
|
/* Some releases of vbios have set DISABLE_MC_MCLKA
|
|
and DISABLE_MC_MCLKB bits in the vbios table. Setting these
|
|
bits will cause H/W hang when reading video memory with dynamic clocking
|
|
enabled. */
|
|
if ((tmp & R300_DISABLE_MC_MCLKA) &&
|
|
(tmp & R300_DISABLE_MC_MCLKB)) {
|
|
/* If both bits are set, then check the active channels */
|
|
tmp = RREG32_PLL(RADEON_MCLK_CNTL);
|
|
if (rdev->mc.vram_width == 64) {
|
|
if (RREG32(RADEON_MEM_CNTL) &
|
|
R300_MEM_USE_CD_CH_ONLY)
|
|
tmp &=
|
|
~R300_DISABLE_MC_MCLKB;
|
|
else
|
|
tmp &=
|
|
~R300_DISABLE_MC_MCLKA;
|
|
} else {
|
|
tmp &= ~(R300_DISABLE_MC_MCLKA |
|
|
R300_DISABLE_MC_MCLKB);
|
|
}
|
|
}
|
|
|
|
WREG32_PLL(RADEON_MCLK_CNTL, tmp);
|
|
} else {
|
|
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
|
|
tmp &= ~(R300_SCLK_FORCE_VAP);
|
|
tmp |= RADEON_SCLK_FORCE_CP;
|
|
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
|
|
mdelay(15);
|
|
|
|
tmp = RREG32_PLL(R300_SCLK_CNTL2);
|
|
tmp &= ~(R300_SCLK_FORCE_TCL |
|
|
R300_SCLK_FORCE_GA |
|
|
R300_SCLK_FORCE_CBA);
|
|
WREG32_PLL(R300_SCLK_CNTL2, tmp);
|
|
}
|
|
} else {
|
|
tmp = RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
|
|
|
|
tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK |
|
|
RADEON_DISP_DYN_STOP_LAT_MASK |
|
|
RADEON_DYN_STOP_MODE_MASK);
|
|
|
|
tmp |= (RADEON_ENGIN_DYNCLK_MODE |
|
|
(0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT));
|
|
WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp);
|
|
mdelay(15);
|
|
|
|
tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
|
|
tmp |= RADEON_SCLK_DYN_START_CNTL;
|
|
WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
|
|
mdelay(15);
|
|
|
|
/* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
|
|
to lockup randomly, leave them as set by BIOS.
|
|
*/
|
|
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
|
|
/*tmp &= RADEON_SCLK_SRC_SEL_MASK; */
|
|
tmp &= ~RADEON_SCLK_FORCEON_MASK;
|
|
|
|
/*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300 */
|
|
if (((rdev->family == CHIP_RV250) &&
|
|
((RREG32(RADEON_CONFIG_CNTL) &
|
|
RADEON_CFG_ATI_REV_ID_MASK) <
|
|
RADEON_CFG_ATI_REV_A13))
|
|
|| ((rdev->family == CHIP_RV100)
|
|
&&
|
|
((RREG32(RADEON_CONFIG_CNTL) &
|
|
RADEON_CFG_ATI_REV_ID_MASK) <=
|
|
RADEON_CFG_ATI_REV_A13))) {
|
|
tmp |= RADEON_SCLK_FORCE_CP;
|
|
tmp |= RADEON_SCLK_FORCE_VIP;
|
|
}
|
|
|
|
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
|
|
|
|
if ((rdev->family == CHIP_RV200) ||
|
|
(rdev->family == CHIP_RV250) ||
|
|
(rdev->family == CHIP_RV280)) {
|
|
tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
|
|
tmp &= ~RADEON_SCLK_MORE_FORCEON;
|
|
|
|
/* RV200::A11 A12 RV250::A11 A12 */
|
|
if (((rdev->family == CHIP_RV200) ||
|
|
(rdev->family == CHIP_RV250)) &&
|
|
((RREG32(RADEON_CONFIG_CNTL) &
|
|
RADEON_CFG_ATI_REV_ID_MASK) <
|
|
RADEON_CFG_ATI_REV_A13)) {
|
|
tmp |= RADEON_SCLK_MORE_FORCEON;
|
|
}
|
|
WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
|
|
mdelay(15);
|
|
}
|
|
|
|
/* RV200::A11 A12, RV250::A11 A12 */
|
|
if (((rdev->family == CHIP_RV200) ||
|
|
(rdev->family == CHIP_RV250)) &&
|
|
((RREG32(RADEON_CONFIG_CNTL) &
|
|
RADEON_CFG_ATI_REV_ID_MASK) <
|
|
RADEON_CFG_ATI_REV_A13)) {
|
|
tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
|
|
tmp |= RADEON_TCL_BYPASS_DISABLE;
|
|
WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
|
|
}
|
|
mdelay(15);
|
|
|
|
/*enable dynamic mode for display clocks (PIXCLK and PIX2CLK) */
|
|
tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
|
|
tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
|
|
RADEON_PIX2CLK_DAC_ALWAYS_ONb |
|
|
RADEON_PIXCLK_BLEND_ALWAYS_ONb |
|
|
RADEON_PIXCLK_GV_ALWAYS_ONb |
|
|
RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
|
|
RADEON_PIXCLK_LVDS_ALWAYS_ONb |
|
|
RADEON_PIXCLK_TMDS_ALWAYS_ONb);
|
|
|
|
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
|
|
mdelay(15);
|
|
|
|
tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
|
|
tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
|
|
RADEON_PIXCLK_DAC_ALWAYS_ONb);
|
|
|
|
WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
|
|
mdelay(15);
|
|
}
|
|
} else {
|
|
/* Turn everything OFF (ForceON to everything) */
|
|
if (rdev->flags & RADEON_SINGLE_CRTC) {
|
|
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
|
|
tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP |
|
|
RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_TOP
|
|
| RADEON_SCLK_FORCE_E2 | RADEON_SCLK_FORCE_SE |
|
|
RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_VIP |
|
|
RADEON_SCLK_FORCE_RE | RADEON_SCLK_FORCE_PB |
|
|
RADEON_SCLK_FORCE_TAM | RADEON_SCLK_FORCE_TDM |
|
|
RADEON_SCLK_FORCE_RB);
|
|
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
|
|
} else if ((rdev->family == CHIP_RS400) ||
|
|
(rdev->family == CHIP_RS480)) {
|
|
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
|
|
tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
|
|
RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1
|
|
| RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 |
|
|
R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT |
|
|
RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
|
|
R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
|
|
R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK |
|
|
R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0);
|
|
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
|
|
|
|
tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
|
|
tmp |= RADEON_SCLK_MORE_FORCEON;
|
|
WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
|
|
|
|
tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
|
|
tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
|
|
RADEON_PIXCLK_DAC_ALWAYS_ONb |
|
|
R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
|
|
WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
|
|
|
|
tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
|
|
tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
|
|
RADEON_PIX2CLK_DAC_ALWAYS_ONb |
|
|
RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
|
|
R300_DVOCLK_ALWAYS_ONb |
|
|
RADEON_PIXCLK_BLEND_ALWAYS_ONb |
|
|
RADEON_PIXCLK_GV_ALWAYS_ONb |
|
|
R300_PIXCLK_DVO_ALWAYS_ONb |
|
|
RADEON_PIXCLK_LVDS_ALWAYS_ONb |
|
|
RADEON_PIXCLK_TMDS_ALWAYS_ONb |
|
|
R300_PIXCLK_TRANS_ALWAYS_ONb |
|
|
R300_PIXCLK_TVO_ALWAYS_ONb |
|
|
R300_P2G2CLK_ALWAYS_ONb |
|
|
R300_P2G2CLK_DAC_ALWAYS_ONb |
|
|
R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
|
|
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
|
|
} else if (rdev->family >= CHIP_RV350) {
|
|
/* for RV350/M10, no delays are required. */
|
|
tmp = RREG32_PLL(R300_SCLK_CNTL2);
|
|
tmp |= (R300_SCLK_FORCE_TCL |
|
|
R300_SCLK_FORCE_GA | R300_SCLK_FORCE_CBA);
|
|
WREG32_PLL(R300_SCLK_CNTL2, tmp);
|
|
|
|
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
|
|
tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
|
|
RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1
|
|
| RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 |
|
|
R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT |
|
|
RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
|
|
R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
|
|
R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK |
|
|
R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0);
|
|
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
|
|
|
|
tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
|
|
tmp |= RADEON_SCLK_MORE_FORCEON;
|
|
WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
|
|
|
|
tmp = RREG32_PLL(RADEON_MCLK_CNTL);
|
|
tmp |= (RADEON_FORCEON_MCLKA |
|
|
RADEON_FORCEON_MCLKB |
|
|
RADEON_FORCEON_YCLKA |
|
|
RADEON_FORCEON_YCLKB | RADEON_FORCEON_MC);
|
|
WREG32_PLL(RADEON_MCLK_CNTL, tmp);
|
|
|
|
tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
|
|
tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
|
|
RADEON_PIXCLK_DAC_ALWAYS_ONb |
|
|
R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
|
|
WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
|
|
|
|
tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
|
|
tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
|
|
RADEON_PIX2CLK_DAC_ALWAYS_ONb |
|
|
RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
|
|
R300_DVOCLK_ALWAYS_ONb |
|
|
RADEON_PIXCLK_BLEND_ALWAYS_ONb |
|
|
RADEON_PIXCLK_GV_ALWAYS_ONb |
|
|
R300_PIXCLK_DVO_ALWAYS_ONb |
|
|
RADEON_PIXCLK_LVDS_ALWAYS_ONb |
|
|
RADEON_PIXCLK_TMDS_ALWAYS_ONb |
|
|
R300_PIXCLK_TRANS_ALWAYS_ONb |
|
|
R300_PIXCLK_TVO_ALWAYS_ONb |
|
|
R300_P2G2CLK_ALWAYS_ONb |
|
|
R300_P2G2CLK_DAC_ALWAYS_ONb |
|
|
R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
|
|
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
|
|
} else {
|
|
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
|
|
tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2);
|
|
tmp |= RADEON_SCLK_FORCE_SE;
|
|
|
|
if (rdev->flags & RADEON_SINGLE_CRTC) {
|
|
tmp |= (RADEON_SCLK_FORCE_RB |
|
|
RADEON_SCLK_FORCE_TDM |
|
|
RADEON_SCLK_FORCE_TAM |
|
|
RADEON_SCLK_FORCE_PB |
|
|
RADEON_SCLK_FORCE_RE |
|
|
RADEON_SCLK_FORCE_VIP |
|
|
RADEON_SCLK_FORCE_IDCT |
|
|
RADEON_SCLK_FORCE_TOP |
|
|
RADEON_SCLK_FORCE_DISP1 |
|
|
RADEON_SCLK_FORCE_DISP2 |
|
|
RADEON_SCLK_FORCE_HDP);
|
|
} else if ((rdev->family == CHIP_R300) ||
|
|
(rdev->family == CHIP_R350)) {
|
|
tmp |= (RADEON_SCLK_FORCE_HDP |
|
|
RADEON_SCLK_FORCE_DISP1 |
|
|
RADEON_SCLK_FORCE_DISP2 |
|
|
RADEON_SCLK_FORCE_TOP |
|
|
RADEON_SCLK_FORCE_IDCT |
|
|
RADEON_SCLK_FORCE_VIP);
|
|
}
|
|
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
|
|
|
|
mdelay(16);
|
|
|
|
if ((rdev->family == CHIP_R300) ||
|
|
(rdev->family == CHIP_R350)) {
|
|
tmp = RREG32_PLL(R300_SCLK_CNTL2);
|
|
tmp |= (R300_SCLK_FORCE_TCL |
|
|
R300_SCLK_FORCE_GA |
|
|
R300_SCLK_FORCE_CBA);
|
|
WREG32_PLL(R300_SCLK_CNTL2, tmp);
|
|
mdelay(16);
|
|
}
|
|
|
|
if (rdev->flags & RADEON_IS_IGP) {
|
|
tmp = RREG32_PLL(RADEON_MCLK_CNTL);
|
|
tmp &= ~(RADEON_FORCEON_MCLKA |
|
|
RADEON_FORCEON_YCLKA);
|
|
WREG32_PLL(RADEON_MCLK_CNTL, tmp);
|
|
mdelay(16);
|
|
}
|
|
|
|
if ((rdev->family == CHIP_RV200) ||
|
|
(rdev->family == CHIP_RV250) ||
|
|
(rdev->family == CHIP_RV280)) {
|
|
tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
|
|
tmp |= RADEON_SCLK_MORE_FORCEON;
|
|
WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
|
|
mdelay(16);
|
|
}
|
|
|
|
tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
|
|
tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
|
|
RADEON_PIX2CLK_DAC_ALWAYS_ONb |
|
|
RADEON_PIXCLK_BLEND_ALWAYS_ONb |
|
|
RADEON_PIXCLK_GV_ALWAYS_ONb |
|
|
RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
|
|
RADEON_PIXCLK_LVDS_ALWAYS_ONb |
|
|
RADEON_PIXCLK_TMDS_ALWAYS_ONb);
|
|
|
|
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
|
|
mdelay(16);
|
|
|
|
tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
|
|
tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
|
|
RADEON_PIXCLK_DAC_ALWAYS_ONb);
|
|
WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
|
|
}
|
|
}
|
|
}
|
|
|