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![Jérome Glisse](/assets/img/avatar_default.png)
I hate doing this but it hurts my eyes to go over code that does not comply with indentation rules. Only thing that is not only space change is in atom.c all other files are space indentation issues. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jérôme Glisse <jglisse@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
319 lines
8.6 KiB
C
319 lines
8.6 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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* Christian König
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*/
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#include <drm/drmP.h>
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#include "radeon.h"
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/*
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* IB
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* IBs (Indirect Buffers) and areas of GPU accessible memory where
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* commands are stored. You can put a pointer to the IB in the
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* command ring and the hw will fetch the commands from the IB
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* and execute them. Generally userspace acceleration drivers
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* produce command buffers which are send to the kernel and
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* put in IBs for execution by the requested ring.
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*/
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static int radeon_debugfs_sa_init(struct radeon_device *rdev);
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/**
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* radeon_ib_get - request an IB (Indirect Buffer)
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*
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* @rdev: radeon_device pointer
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* @ring: ring index the IB is associated with
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* @ib: IB object returned
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* @size: requested IB size
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*
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* Request an IB (all asics). IBs are allocated using the
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* suballocator.
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* Returns 0 on success, error on failure.
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*/
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int radeon_ib_get(struct radeon_device *rdev, int ring,
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struct radeon_ib *ib, struct radeon_vm *vm,
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unsigned size)
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{
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int r;
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r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256);
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if (r) {
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dev_err(rdev->dev, "failed to get a new IB (%d)\n", r);
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return r;
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}
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radeon_sync_create(&ib->sync);
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ib->ring = ring;
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ib->fence = NULL;
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ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo);
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ib->vm = vm;
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if (vm) {
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/* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address
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* space and soffset is the offset inside the pool bo
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*/
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ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET;
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} else {
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ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo);
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}
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ib->is_const_ib = false;
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return 0;
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}
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/**
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* radeon_ib_free - free an IB (Indirect Buffer)
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*
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* @rdev: radeon_device pointer
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* @ib: IB object to free
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*
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* Free an IB (all asics).
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*/
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void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib)
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{
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radeon_sync_free(rdev, &ib->sync, ib->fence);
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radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence);
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radeon_fence_unref(&ib->fence);
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}
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/**
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* radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring
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*
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* @rdev: radeon_device pointer
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* @ib: IB object to schedule
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* @const_ib: Const IB to schedule (SI only)
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* @hdp_flush: Whether or not to perform an HDP cache flush
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*
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* Schedule an IB on the associated ring (all asics).
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* Returns 0 on success, error on failure.
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*
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* On SI, there are two parallel engines fed from the primary ring,
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* the CE (Constant Engine) and the DE (Drawing Engine). Since
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* resource descriptors have moved to memory, the CE allows you to
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* prime the caches while the DE is updating register state so that
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* the resource descriptors will be already in cache when the draw is
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* processed. To accomplish this, the userspace driver submits two
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* IBs, one for the CE and one for the DE. If there is a CE IB (called
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* a CONST_IB), it will be put on the ring prior to the DE IB. Prior
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* to SI there was just a DE IB.
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*/
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int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
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struct radeon_ib *const_ib, bool hdp_flush)
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{
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struct radeon_ring *ring = &rdev->ring[ib->ring];
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int r = 0;
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if (!ib->length_dw || !ring->ready) {
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/* TODO: Nothings in the ib we should report. */
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dev_err(rdev->dev, "couldn't schedule ib\n");
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return -EINVAL;
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}
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/* 64 dwords should be enough for fence too */
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r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_SYNCS * 8);
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if (r) {
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dev_err(rdev->dev, "scheduling IB failed (%d).\n", r);
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return r;
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}
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/* grab a vm id if necessary */
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if (ib->vm) {
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struct radeon_fence *vm_id_fence;
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vm_id_fence = radeon_vm_grab_id(rdev, ib->vm, ib->ring);
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radeon_sync_fence(&ib->sync, vm_id_fence);
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}
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/* sync with other rings */
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r = radeon_sync_rings(rdev, &ib->sync, ib->ring);
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if (r) {
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dev_err(rdev->dev, "failed to sync rings (%d)\n", r);
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radeon_ring_unlock_undo(rdev, ring);
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return r;
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}
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if (ib->vm)
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radeon_vm_flush(rdev, ib->vm, ib->ring,
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ib->sync.last_vm_update);
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if (const_ib) {
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radeon_ring_ib_execute(rdev, const_ib->ring, const_ib);
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radeon_sync_free(rdev, &const_ib->sync, NULL);
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}
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radeon_ring_ib_execute(rdev, ib->ring, ib);
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r = radeon_fence_emit(rdev, &ib->fence, ib->ring);
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if (r) {
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dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r);
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radeon_ring_unlock_undo(rdev, ring);
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return r;
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}
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if (const_ib) {
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const_ib->fence = radeon_fence_ref(ib->fence);
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}
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if (ib->vm)
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radeon_vm_fence(rdev, ib->vm, ib->fence);
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radeon_ring_unlock_commit(rdev, ring, hdp_flush);
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return 0;
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}
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/**
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* radeon_ib_pool_init - Init the IB (Indirect Buffer) pool
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*
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* @rdev: radeon_device pointer
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*
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* Initialize the suballocator to manage a pool of memory
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* for use as IBs (all asics).
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* Returns 0 on success, error on failure.
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*/
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int radeon_ib_pool_init(struct radeon_device *rdev)
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{
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int r;
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if (rdev->ib_pool_ready) {
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return 0;
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}
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if (rdev->family >= CHIP_BONAIRE) {
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r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
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RADEON_IB_POOL_SIZE*64*1024,
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RADEON_GPU_PAGE_SIZE,
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RADEON_GEM_DOMAIN_GTT,
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RADEON_GEM_GTT_WC);
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} else {
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/* Before CIK, it's better to stick to cacheable GTT due
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* to the command stream checking
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*/
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r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
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RADEON_IB_POOL_SIZE*64*1024,
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RADEON_GPU_PAGE_SIZE,
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RADEON_GEM_DOMAIN_GTT, 0);
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}
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if (r) {
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return r;
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}
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r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo);
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if (r) {
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return r;
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}
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rdev->ib_pool_ready = true;
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if (radeon_debugfs_sa_init(rdev)) {
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dev_err(rdev->dev, "failed to register debugfs file for SA\n");
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}
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return 0;
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}
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/**
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* radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool
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*
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* @rdev: radeon_device pointer
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*
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* Tear down the suballocator managing the pool of memory
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* for use as IBs (all asics).
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*/
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void radeon_ib_pool_fini(struct radeon_device *rdev)
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{
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if (rdev->ib_pool_ready) {
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radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo);
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radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo);
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rdev->ib_pool_ready = false;
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}
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}
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/**
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* radeon_ib_ring_tests - test IBs on the rings
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*
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* @rdev: radeon_device pointer
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*
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* Test an IB (Indirect Buffer) on each ring.
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* If the test fails, disable the ring.
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* Returns 0 on success, error if the primary GFX ring
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* IB test fails.
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*/
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int radeon_ib_ring_tests(struct radeon_device *rdev)
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{
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unsigned i;
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int r;
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for (i = 0; i < RADEON_NUM_RINGS; ++i) {
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struct radeon_ring *ring = &rdev->ring[i];
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if (!ring->ready)
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continue;
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r = radeon_ib_test(rdev, i, ring);
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if (r) {
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radeon_fence_driver_force_completion(rdev, i);
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ring->ready = false;
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rdev->needs_reset = false;
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if (i == RADEON_RING_TYPE_GFX_INDEX) {
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/* oh, oh, that's really bad */
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DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r);
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rdev->accel_working = false;
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return r;
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} else {
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/* still not good, but we can live with it */
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DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r);
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}
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}
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}
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return 0;
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}
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/*
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* Debugfs info
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*/
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#if defined(CONFIG_DEBUG_FS)
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static int radeon_debugfs_sa_info(struct seq_file *m, void *data)
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{
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struct drm_info_node *node = (struct drm_info_node *) m->private;
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struct drm_device *dev = node->minor->dev;
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struct radeon_device *rdev = dev->dev_private;
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radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m);
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return 0;
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}
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static struct drm_info_list radeon_debugfs_sa_list[] = {
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{"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL},
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};
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#endif
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static int radeon_debugfs_sa_init(struct radeon_device *rdev)
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{
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#if defined(CONFIG_DEBUG_FS)
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return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1);
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#else
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return 0;
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#endif
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}
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