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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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877fa9a42d
This set of changes contains a bunch of cleanups to the host1x driver as well as the addition of a pin controller for DPAUX, which is required by boards to configure the DPAUX pads in AUX mode (for DisplayPort) or I2C mode (for HDMI and DDC). Included is also a bit of rework of the SOR driver in preparation to add DisplayPort support as well as some refactoring and cleanup. Finally, all output drivers are converted to runtime PM, which greatly simplifies the handling of clocks and resets. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJXh5n1AAoJEN0jrNd/PrOh+KcP/0SLO9UKvGBsfD0EFvkxx/NV VZvqCWP0ARCGDAZn890O4sqwgHdRDF+hp0HcUt8wDt4o3VTYJIdifr/5tunOZ6+w 1IatWrjJjpyvZs9bveEvtJ8Hbkq5h0esA1StcqheRUiE0o+uQppdWO1NLO+HxssQ f4qV4GQ7trJQdjr9OGfGJigsvOjwGVbPL7CRrKKLmbfTiqy9zhi5bOyUfojtMEL6 BvH9RMqC0ke70sGtcPgigbL7wgnbkH0uR3sV5TwU5dErrvh0tnhYU1a1ednPotJW z56+W8hWfC3XLIiU9mju1l+3sQA0BuS9ZQ+6VhdRTKxv85CUI5dUKT0/h5BtRrK9 0XgPwrn4YpAr17oFEGdqFPhefkDkbb/1WrWmgUEi8/YaimdCXNkf8rILZvWUVQdt q9GbbmEiGNR2FvBEN7s/nT96E5XEzfLTjOzTOP0c5RF9cOK+Ul9t0t44eBn4Wqbk x6rTv37eieK5RVYd24xKKnzf5uSMpU+RTea4Vpr0xdH6glGcrTJ5ogub0iIsY0Jn A9M1pKadQvu//95ZzGWEyrqAr66cDG8vGjZn9z24PRaNZEbzvY3ohj2/qOSQoRFY HPmswshI0DnyFPWmdhhlPy3di0zNDP6kfPo6NhotoAl2Uwd+RrY/VyWjDG0dwV0R nSkcnGES5hnf3gguXEmO =7xlG -----END PGP SIGNATURE----- Merge tag 'drm/tegra/for-4.8-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next drm/tegra: Changes for v4.8-rc1 This set of changes contains a bunch of cleanups to the host1x driver as well as the addition of a pin controller for DPAUX, which is required by boards to configure the DPAUX pads in AUX mode (for DisplayPort) or I2C mode (for HDMI and DDC). Included is also a bit of rework of the SOR driver in preparation to add DisplayPort support as well as some refactoring and cleanup. Finally, all output drivers are converted to runtime PM, which greatly simplifies the handling of clocks and resets. * tag 'drm/tegra/for-4.8-rc1' of git://anongit.freedesktop.org/tegra/linux: (35 commits) drm/tegra: sor: Reject HDMI 2.0 modes drm/tegra: sor: Prepare for generic PM domain support drm/tegra: dsi: Prepare for generic PM domain support drm/tegra: sor: Make XBAR configurable per SoC drm/tegra: sor: Use sor1_src clock to set parent for HDMI dt-bindings: display: tegra: Add source clock for SOR drm/tegra: sor: Implement sor1_brick clock drm/tegra: sor: Implement runtime PM drm/tegra: hdmi: Implement runtime PM drm/tegra: dsi: Implement runtime PM drm/tegra: dc: Implement runtime PM drm/tegra: hdmi: Enable audio over HDMI drm/tegra: sor: Do not support deep color modes drm/tegra: sor: Extract tegra_sor_mode_set() drm/tegra: sor: Split out tegra_sor_apply_config() drm/tegra: sor: Rename tegra_sor_calc_config() drm/tegra: sor: Factor out tegra_sor_set_parent_clock() drm/tegra: dpaux: Add pinctrl support dt-bindings: Add bindings for Tegra DPAUX pinctrl driver drm/tegra: Prepare DPAUX for supporting generic PM domains ...
1839 lines
53 KiB
C
1839 lines
53 KiB
C
/*
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* Copyright (C) 2012 Avionic Design GmbH
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* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/debugfs.h>
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#include <linux/gpio.h>
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#include <linux/hdmi.h>
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#include <linux/pm_runtime.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <sound/hda_verbs.h>
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#include "hdmi.h"
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#include "drm.h"
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#include "dc.h"
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#define HDMI_ELD_BUFFER_SIZE 96
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struct tmds_config {
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unsigned int pclk;
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u32 pll0;
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u32 pll1;
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u32 pe_current;
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u32 drive_current;
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u32 peak_current;
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};
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struct tegra_hdmi_config {
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const struct tmds_config *tmds;
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unsigned int num_tmds;
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unsigned long fuse_override_offset;
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u32 fuse_override_value;
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bool has_sor_io_peak_current;
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bool has_hda;
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bool has_hbr;
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};
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struct tegra_hdmi {
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struct host1x_client client;
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struct tegra_output output;
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struct device *dev;
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struct regulator *hdmi;
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struct regulator *pll;
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struct regulator *vdd;
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void __iomem *regs;
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unsigned int irq;
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struct clk *clk_parent;
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struct clk *clk;
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struct reset_control *rst;
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const struct tegra_hdmi_config *config;
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unsigned int audio_source;
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unsigned int audio_sample_rate;
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unsigned int audio_channels;
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unsigned int pixel_clock;
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bool stereo;
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bool dvi;
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struct drm_info_list *debugfs_files;
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struct drm_minor *minor;
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struct dentry *debugfs;
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};
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static inline struct tegra_hdmi *
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host1x_client_to_hdmi(struct host1x_client *client)
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{
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return container_of(client, struct tegra_hdmi, client);
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}
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static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
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{
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return container_of(output, struct tegra_hdmi, output);
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}
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#define HDMI_AUDIOCLK_FREQ 216000000
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#define HDMI_REKEY_DEFAULT 56
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enum {
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AUTO = 0,
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SPDIF,
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HDA,
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};
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static inline u32 tegra_hdmi_readl(struct tegra_hdmi *hdmi,
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unsigned long offset)
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{
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return readl(hdmi->regs + (offset << 2));
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}
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static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value,
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unsigned long offset)
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{
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writel(value, hdmi->regs + (offset << 2));
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}
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struct tegra_hdmi_audio_config {
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unsigned int pclk;
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unsigned int n;
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unsigned int cts;
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unsigned int aval;
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};
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static const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
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{ 25200000, 4096, 25200, 24000 },
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{ 27000000, 4096, 27000, 24000 },
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{ 74250000, 4096, 74250, 24000 },
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{ 148500000, 4096, 148500, 24000 },
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{ 0, 0, 0, 0 },
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};
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static const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
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{ 25200000, 5880, 26250, 25000 },
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{ 27000000, 5880, 28125, 25000 },
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{ 74250000, 4704, 61875, 20000 },
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{ 148500000, 4704, 123750, 20000 },
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{ 0, 0, 0, 0 },
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};
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static const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
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{ 25200000, 6144, 25200, 24000 },
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{ 27000000, 6144, 27000, 24000 },
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{ 74250000, 6144, 74250, 24000 },
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{ 148500000, 6144, 148500, 24000 },
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{ 0, 0, 0, 0 },
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};
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static const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = {
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{ 25200000, 11760, 26250, 25000 },
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{ 27000000, 11760, 28125, 25000 },
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{ 74250000, 9408, 61875, 20000 },
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{ 148500000, 9408, 123750, 20000 },
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{ 0, 0, 0, 0 },
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};
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static const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = {
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{ 25200000, 12288, 25200, 24000 },
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{ 27000000, 12288, 27000, 24000 },
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{ 74250000, 12288, 74250, 24000 },
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{ 148500000, 12288, 148500, 24000 },
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{ 0, 0, 0, 0 },
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};
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static const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = {
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{ 25200000, 23520, 26250, 25000 },
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{ 27000000, 23520, 28125, 25000 },
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{ 74250000, 18816, 61875, 20000 },
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{ 148500000, 18816, 123750, 20000 },
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{ 0, 0, 0, 0 },
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};
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static const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = {
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{ 25200000, 24576, 25200, 24000 },
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{ 27000000, 24576, 27000, 24000 },
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{ 74250000, 24576, 74250, 24000 },
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{ 148500000, 24576, 148500, 24000 },
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{ 0, 0, 0, 0 },
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};
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static const struct tmds_config tegra20_tmds_config[] = {
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{ /* slow pixel clock modes */
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.pclk = 27000000,
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.pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
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SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
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SOR_PLL_TX_REG_LOAD(3),
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.pll1 = SOR_PLL_TMDS_TERM_ENABLE,
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.pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
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PE_CURRENT1(PE_CURRENT_0_0_mA) |
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PE_CURRENT2(PE_CURRENT_0_0_mA) |
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PE_CURRENT3(PE_CURRENT_0_0_mA),
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.drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
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DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
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DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
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DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
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},
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{ /* high pixel clock modes */
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.pclk = UINT_MAX,
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.pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
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SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
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SOR_PLL_TX_REG_LOAD(3),
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.pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
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.pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
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PE_CURRENT1(PE_CURRENT_6_0_mA) |
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PE_CURRENT2(PE_CURRENT_6_0_mA) |
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PE_CURRENT3(PE_CURRENT_6_0_mA),
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.drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
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DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
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DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
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DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
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},
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};
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static const struct tmds_config tegra30_tmds_config[] = {
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{ /* 480p modes */
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.pclk = 27000000,
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.pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
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SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
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SOR_PLL_TX_REG_LOAD(0),
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.pll1 = SOR_PLL_TMDS_TERM_ENABLE,
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.pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
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PE_CURRENT1(PE_CURRENT_0_0_mA) |
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PE_CURRENT2(PE_CURRENT_0_0_mA) |
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PE_CURRENT3(PE_CURRENT_0_0_mA),
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.drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
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DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
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DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
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DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
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}, { /* 720p modes */
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.pclk = 74250000,
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.pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
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SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
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SOR_PLL_TX_REG_LOAD(0),
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.pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
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.pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
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PE_CURRENT1(PE_CURRENT_5_0_mA) |
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PE_CURRENT2(PE_CURRENT_5_0_mA) |
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PE_CURRENT3(PE_CURRENT_5_0_mA),
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.drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
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DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
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DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
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DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
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}, { /* 1080p modes */
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.pclk = UINT_MAX,
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.pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
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SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
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SOR_PLL_TX_REG_LOAD(0),
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.pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
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.pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
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PE_CURRENT1(PE_CURRENT_5_0_mA) |
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PE_CURRENT2(PE_CURRENT_5_0_mA) |
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PE_CURRENT3(PE_CURRENT_5_0_mA),
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.drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
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DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
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DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
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DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
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},
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};
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static const struct tmds_config tegra114_tmds_config[] = {
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{ /* 480p/576p / 25.2MHz/27MHz modes */
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.pclk = 27000000,
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.pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
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SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
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.pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
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.pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
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PE_CURRENT1(PE_CURRENT_0_mA_T114) |
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PE_CURRENT2(PE_CURRENT_0_mA_T114) |
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PE_CURRENT3(PE_CURRENT_0_mA_T114),
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.drive_current =
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DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
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DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
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DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
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DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
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.peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
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PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
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PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
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PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
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}, { /* 720p / 74.25MHz modes */
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.pclk = 74250000,
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.pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
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SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
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.pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
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SOR_PLL_TMDS_TERMADJ(0),
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.pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
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PE_CURRENT1(PE_CURRENT_15_mA_T114) |
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PE_CURRENT2(PE_CURRENT_15_mA_T114) |
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PE_CURRENT3(PE_CURRENT_15_mA_T114),
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.drive_current =
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DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
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DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
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DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
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DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
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.peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
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PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
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PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
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PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
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}, { /* 1080p / 148.5MHz modes */
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.pclk = 148500000,
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.pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
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SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
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.pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
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SOR_PLL_TMDS_TERMADJ(0),
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.pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
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PE_CURRENT1(PE_CURRENT_10_mA_T114) |
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PE_CURRENT2(PE_CURRENT_10_mA_T114) |
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PE_CURRENT3(PE_CURRENT_10_mA_T114),
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.drive_current =
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DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
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DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
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DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
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DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
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.peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
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PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
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PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
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PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
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}, { /* 225/297MHz modes */
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.pclk = UINT_MAX,
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.pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
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SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
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.pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
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| SOR_PLL_TMDS_TERM_ENABLE,
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.pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
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PE_CURRENT1(PE_CURRENT_0_mA_T114) |
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PE_CURRENT2(PE_CURRENT_0_mA_T114) |
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PE_CURRENT3(PE_CURRENT_0_mA_T114),
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.drive_current =
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DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
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DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
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DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
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DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
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.peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
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PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
|
|
PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
|
|
PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
|
|
},
|
|
};
|
|
|
|
static const struct tmds_config tegra124_tmds_config[] = {
|
|
{ /* 480p/576p / 25.2MHz/27MHz modes */
|
|
.pclk = 27000000,
|
|
.pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
|
|
SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
|
|
.pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
|
|
.pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
|
|
PE_CURRENT1(PE_CURRENT_0_mA_T114) |
|
|
PE_CURRENT2(PE_CURRENT_0_mA_T114) |
|
|
PE_CURRENT3(PE_CURRENT_0_mA_T114),
|
|
.drive_current =
|
|
DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
|
|
DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
|
|
DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
|
|
DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
|
|
.peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
|
|
PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
|
|
PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
|
|
PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
|
|
}, { /* 720p / 74.25MHz modes */
|
|
.pclk = 74250000,
|
|
.pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
|
|
SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
|
|
.pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
|
|
SOR_PLL_TMDS_TERMADJ(0),
|
|
.pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
|
|
PE_CURRENT1(PE_CURRENT_15_mA_T114) |
|
|
PE_CURRENT2(PE_CURRENT_15_mA_T114) |
|
|
PE_CURRENT3(PE_CURRENT_15_mA_T114),
|
|
.drive_current =
|
|
DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
|
|
DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
|
|
DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
|
|
DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
|
|
.peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
|
|
PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
|
|
PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
|
|
PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
|
|
}, { /* 1080p / 148.5MHz modes */
|
|
.pclk = 148500000,
|
|
.pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
|
|
SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
|
|
.pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
|
|
SOR_PLL_TMDS_TERMADJ(0),
|
|
.pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
|
|
PE_CURRENT1(PE_CURRENT_10_mA_T114) |
|
|
PE_CURRENT2(PE_CURRENT_10_mA_T114) |
|
|
PE_CURRENT3(PE_CURRENT_10_mA_T114),
|
|
.drive_current =
|
|
DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
|
|
DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
|
|
DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
|
|
DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
|
|
.peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
|
|
PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
|
|
PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
|
|
PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
|
|
}, { /* 225/297MHz modes */
|
|
.pclk = UINT_MAX,
|
|
.pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
|
|
SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
|
|
.pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
|
|
| SOR_PLL_TMDS_TERM_ENABLE,
|
|
.pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
|
|
PE_CURRENT1(PE_CURRENT_0_mA_T114) |
|
|
PE_CURRENT2(PE_CURRENT_0_mA_T114) |
|
|
PE_CURRENT3(PE_CURRENT_0_mA_T114),
|
|
.drive_current =
|
|
DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
|
|
DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
|
|
DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
|
|
DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
|
|
.peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
|
|
PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
|
|
PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
|
|
PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
|
|
},
|
|
};
|
|
|
|
static const struct tegra_hdmi_audio_config *
|
|
tegra_hdmi_get_audio_config(unsigned int sample_rate, unsigned int pclk)
|
|
{
|
|
const struct tegra_hdmi_audio_config *table;
|
|
|
|
switch (sample_rate) {
|
|
case 32000:
|
|
table = tegra_hdmi_audio_32k;
|
|
break;
|
|
|
|
case 44100:
|
|
table = tegra_hdmi_audio_44_1k;
|
|
break;
|
|
|
|
case 48000:
|
|
table = tegra_hdmi_audio_48k;
|
|
break;
|
|
|
|
case 88200:
|
|
table = tegra_hdmi_audio_88_2k;
|
|
break;
|
|
|
|
case 96000:
|
|
table = tegra_hdmi_audio_96k;
|
|
break;
|
|
|
|
case 176400:
|
|
table = tegra_hdmi_audio_176_4k;
|
|
break;
|
|
|
|
case 192000:
|
|
table = tegra_hdmi_audio_192k;
|
|
break;
|
|
|
|
default:
|
|
return NULL;
|
|
}
|
|
|
|
while (table->pclk) {
|
|
if (table->pclk == pclk)
|
|
return table;
|
|
|
|
table++;
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
|
|
{
|
|
const unsigned int freqs[] = {
|
|
32000, 44100, 48000, 88200, 96000, 176400, 192000
|
|
};
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(freqs); i++) {
|
|
unsigned int f = freqs[i];
|
|
unsigned int eight_half;
|
|
unsigned int delta;
|
|
u32 value;
|
|
|
|
if (f > 96000)
|
|
delta = 2;
|
|
else if (f > 48000)
|
|
delta = 6;
|
|
else
|
|
delta = 9;
|
|
|
|
eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
|
|
value = AUDIO_FS_LOW(eight_half - delta) |
|
|
AUDIO_FS_HIGH(eight_half + delta);
|
|
tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
|
|
}
|
|
}
|
|
|
|
static void tegra_hdmi_write_aval(struct tegra_hdmi *hdmi, u32 value)
|
|
{
|
|
static const struct {
|
|
unsigned int sample_rate;
|
|
unsigned int offset;
|
|
} regs[] = {
|
|
{ 32000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 },
|
|
{ 44100, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 },
|
|
{ 48000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 },
|
|
{ 88200, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 },
|
|
{ 96000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 },
|
|
{ 176400, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 },
|
|
{ 192000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 },
|
|
};
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(regs); i++) {
|
|
if (regs[i].sample_rate == hdmi->audio_sample_rate) {
|
|
tegra_hdmi_writel(hdmi, value, regs[i].offset);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi)
|
|
{
|
|
const struct tegra_hdmi_audio_config *config;
|
|
u32 source, value;
|
|
|
|
switch (hdmi->audio_source) {
|
|
case HDA:
|
|
if (hdmi->config->has_hda)
|
|
source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
|
|
else
|
|
return -EINVAL;
|
|
|
|
break;
|
|
|
|
case SPDIF:
|
|
if (hdmi->config->has_hda)
|
|
source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
|
|
else
|
|
source = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
|
|
break;
|
|
|
|
default:
|
|
if (hdmi->config->has_hda)
|
|
source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
|
|
else
|
|
source = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* Tegra30 and later use a slightly modified version of the register
|
|
* layout to accomodate for changes related to supporting HDA as the
|
|
* audio input source for HDMI. The source select field has moved to
|
|
* the SOR_AUDIO_CNTRL0 register, but the error tolerance and frames
|
|
* per block fields remain in the AUDIO_CNTRL0 register.
|
|
*/
|
|
if (hdmi->config->has_hda) {
|
|
/*
|
|
* Inject null samples into the audio FIFO for every frame in
|
|
* which the codec did not receive any samples. This applies
|
|
* to stereo LPCM only.
|
|
*
|
|
* XXX: This seems to be a remnant of MCP days when this was
|
|
* used to work around issues with monitors not being able to
|
|
* play back system startup sounds early. It is possibly not
|
|
* needed on Linux at all.
|
|
*/
|
|
if (hdmi->audio_channels == 2)
|
|
value = SOR_AUDIO_CNTRL0_INJECT_NULLSMPL;
|
|
else
|
|
value = 0;
|
|
|
|
value |= source;
|
|
|
|
tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
|
|
}
|
|
|
|
/*
|
|
* On Tegra20, HDA is not a supported audio source and the source
|
|
* select field is part of the AUDIO_CNTRL0 register.
|
|
*/
|
|
value = AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) |
|
|
AUDIO_CNTRL0_ERROR_TOLERANCE(6);
|
|
|
|
if (!hdmi->config->has_hda)
|
|
value |= source;
|
|
|
|
tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
|
|
|
|
/*
|
|
* Advertise support for High Bit-Rate on Tegra114 and later.
|
|
*/
|
|
if (hdmi->config->has_hbr) {
|
|
value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
|
|
value |= SOR_AUDIO_SPARE0_HBR_ENABLE;
|
|
tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
|
|
}
|
|
|
|
config = tegra_hdmi_get_audio_config(hdmi->audio_sample_rate,
|
|
hdmi->pixel_clock);
|
|
if (!config) {
|
|
dev_err(hdmi->dev,
|
|
"cannot set audio to %u Hz at %u Hz pixel clock\n",
|
|
hdmi->audio_sample_rate, hdmi->pixel_clock);
|
|
return -EINVAL;
|
|
}
|
|
|
|
tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
|
|
|
|
value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
|
|
AUDIO_N_VALUE(config->n - 1);
|
|
tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
|
|
|
|
tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
|
|
HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
|
|
|
|
tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config->cts),
|
|
HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
|
|
|
|
value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
|
|
tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
|
|
|
|
value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
|
|
value &= ~AUDIO_N_RESETF;
|
|
tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
|
|
|
|
if (hdmi->config->has_hda)
|
|
tegra_hdmi_write_aval(hdmi, config->aval);
|
|
|
|
tegra_hdmi_setup_audio_fs_tables(hdmi);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void tegra_hdmi_disable_audio(struct tegra_hdmi *hdmi)
|
|
{
|
|
u32 value;
|
|
|
|
value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
|
|
value &= ~GENERIC_CTRL_AUDIO;
|
|
tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
|
|
}
|
|
|
|
static void tegra_hdmi_enable_audio(struct tegra_hdmi *hdmi)
|
|
{
|
|
u32 value;
|
|
|
|
value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
|
|
value |= GENERIC_CTRL_AUDIO;
|
|
tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
|
|
}
|
|
|
|
static void tegra_hdmi_write_eld(struct tegra_hdmi *hdmi)
|
|
{
|
|
size_t length = drm_eld_size(hdmi->output.connector.eld), i;
|
|
u32 value;
|
|
|
|
for (i = 0; i < length; i++)
|
|
tegra_hdmi_writel(hdmi, i << 8 | hdmi->output.connector.eld[i],
|
|
HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
|
|
|
|
/*
|
|
* The HDA codec will always report an ELD buffer size of 96 bytes and
|
|
* the HDA codec driver will check that each byte read from the buffer
|
|
* is valid. Therefore every byte must be written, even if no 96 bytes
|
|
* were parsed from EDID.
|
|
*/
|
|
for (i = length; i < HDMI_ELD_BUFFER_SIZE; i++)
|
|
tegra_hdmi_writel(hdmi, i << 8 | 0,
|
|
HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
|
|
|
|
value = SOR_AUDIO_HDA_PRESENSE_VALID | SOR_AUDIO_HDA_PRESENSE_PRESENT;
|
|
tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
|
|
}
|
|
|
|
static inline u32 tegra_hdmi_subpack(const u8 *ptr, size_t size)
|
|
{
|
|
u32 value = 0;
|
|
size_t i;
|
|
|
|
for (i = size; i > 0; i--)
|
|
value = (value << 8) | ptr[i - 1];
|
|
|
|
return value;
|
|
}
|
|
|
|
static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data,
|
|
size_t size)
|
|
{
|
|
const u8 *ptr = data;
|
|
unsigned long offset;
|
|
size_t i, j;
|
|
u32 value;
|
|
|
|
switch (ptr[0]) {
|
|
case HDMI_INFOFRAME_TYPE_AVI:
|
|
offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER;
|
|
break;
|
|
|
|
case HDMI_INFOFRAME_TYPE_AUDIO:
|
|
offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER;
|
|
break;
|
|
|
|
case HDMI_INFOFRAME_TYPE_VENDOR:
|
|
offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER;
|
|
break;
|
|
|
|
default:
|
|
dev_err(hdmi->dev, "unsupported infoframe type: %02x\n",
|
|
ptr[0]);
|
|
return;
|
|
}
|
|
|
|
value = INFOFRAME_HEADER_TYPE(ptr[0]) |
|
|
INFOFRAME_HEADER_VERSION(ptr[1]) |
|
|
INFOFRAME_HEADER_LEN(ptr[2]);
|
|
tegra_hdmi_writel(hdmi, value, offset);
|
|
offset++;
|
|
|
|
/*
|
|
* Each subpack contains 7 bytes, divided into:
|
|
* - subpack_low: bytes 0 - 3
|
|
* - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
|
|
*/
|
|
for (i = 3, j = 0; i < size; i += 7, j += 8) {
|
|
size_t rem = size - i, num = min_t(size_t, rem, 4);
|
|
|
|
value = tegra_hdmi_subpack(&ptr[i], num);
|
|
tegra_hdmi_writel(hdmi, value, offset++);
|
|
|
|
num = min_t(size_t, rem - num, 3);
|
|
|
|
value = tegra_hdmi_subpack(&ptr[i + 4], num);
|
|
tegra_hdmi_writel(hdmi, value, offset++);
|
|
}
|
|
}
|
|
|
|
static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
|
|
struct drm_display_mode *mode)
|
|
{
|
|
struct hdmi_avi_infoframe frame;
|
|
u8 buffer[17];
|
|
ssize_t err;
|
|
|
|
err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
|
|
if (err < 0) {
|
|
dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err);
|
|
return;
|
|
}
|
|
|
|
err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
|
|
if (err < 0) {
|
|
dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err);
|
|
return;
|
|
}
|
|
|
|
tegra_hdmi_write_infopack(hdmi, buffer, err);
|
|
}
|
|
|
|
static void tegra_hdmi_disable_avi_infoframe(struct tegra_hdmi *hdmi)
|
|
{
|
|
u32 value;
|
|
|
|
value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
|
|
value &= ~INFOFRAME_CTRL_ENABLE;
|
|
tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
|
|
}
|
|
|
|
static void tegra_hdmi_enable_avi_infoframe(struct tegra_hdmi *hdmi)
|
|
{
|
|
u32 value;
|
|
|
|
value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
|
|
value |= INFOFRAME_CTRL_ENABLE;
|
|
tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
|
|
}
|
|
|
|
static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
|
|
{
|
|
struct hdmi_audio_infoframe frame;
|
|
u8 buffer[14];
|
|
ssize_t err;
|
|
|
|
err = hdmi_audio_infoframe_init(&frame);
|
|
if (err < 0) {
|
|
dev_err(hdmi->dev, "failed to setup audio infoframe: %zd\n",
|
|
err);
|
|
return;
|
|
}
|
|
|
|
frame.channels = hdmi->audio_channels;
|
|
|
|
err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
|
|
if (err < 0) {
|
|
dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n",
|
|
err);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* The audio infoframe has only one set of subpack registers, so the
|
|
* infoframe needs to be truncated. One set of subpack registers can
|
|
* contain 7 bytes. Including the 3 byte header only the first 10
|
|
* bytes can be programmed.
|
|
*/
|
|
tegra_hdmi_write_infopack(hdmi, buffer, min_t(size_t, 10, err));
|
|
}
|
|
|
|
static void tegra_hdmi_disable_audio_infoframe(struct tegra_hdmi *hdmi)
|
|
{
|
|
u32 value;
|
|
|
|
value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
|
|
value &= ~INFOFRAME_CTRL_ENABLE;
|
|
tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
|
|
}
|
|
|
|
static void tegra_hdmi_enable_audio_infoframe(struct tegra_hdmi *hdmi)
|
|
{
|
|
u32 value;
|
|
|
|
value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
|
|
value |= INFOFRAME_CTRL_ENABLE;
|
|
tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
|
|
}
|
|
|
|
static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
|
|
{
|
|
struct hdmi_vendor_infoframe frame;
|
|
u8 buffer[10];
|
|
ssize_t err;
|
|
|
|
hdmi_vendor_infoframe_init(&frame);
|
|
frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING;
|
|
|
|
err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
|
|
if (err < 0) {
|
|
dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n",
|
|
err);
|
|
return;
|
|
}
|
|
|
|
tegra_hdmi_write_infopack(hdmi, buffer, err);
|
|
}
|
|
|
|
static void tegra_hdmi_disable_stereo_infoframe(struct tegra_hdmi *hdmi)
|
|
{
|
|
u32 value;
|
|
|
|
value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
|
|
value &= ~GENERIC_CTRL_ENABLE;
|
|
tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
|
|
}
|
|
|
|
static void tegra_hdmi_enable_stereo_infoframe(struct tegra_hdmi *hdmi)
|
|
{
|
|
u32 value;
|
|
|
|
value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
|
|
value |= GENERIC_CTRL_ENABLE;
|
|
tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
|
|
}
|
|
|
|
static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
|
|
const struct tmds_config *tmds)
|
|
{
|
|
u32 value;
|
|
|
|
tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
|
|
tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
|
|
tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
|
|
|
|
tegra_hdmi_writel(hdmi, tmds->drive_current,
|
|
HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
|
|
|
|
value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset);
|
|
value |= hdmi->config->fuse_override_value;
|
|
tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset);
|
|
|
|
if (hdmi->config->has_sor_io_peak_current)
|
|
tegra_hdmi_writel(hdmi, tmds->peak_current,
|
|
HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
|
|
}
|
|
|
|
static bool tegra_output_is_hdmi(struct tegra_output *output)
|
|
{
|
|
struct edid *edid;
|
|
|
|
if (!output->connector.edid_blob_ptr)
|
|
return false;
|
|
|
|
edid = (struct edid *)output->connector.edid_blob_ptr->data;
|
|
|
|
return drm_detect_hdmi_monitor(edid);
|
|
}
|
|
|
|
static enum drm_connector_status
|
|
tegra_hdmi_connector_detect(struct drm_connector *connector, bool force)
|
|
{
|
|
struct tegra_output *output = connector_to_output(connector);
|
|
struct tegra_hdmi *hdmi = to_hdmi(output);
|
|
enum drm_connector_status status;
|
|
|
|
status = tegra_output_connector_detect(connector, force);
|
|
if (status == connector_status_connected)
|
|
return status;
|
|
|
|
tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
|
|
return status;
|
|
}
|
|
|
|
static const struct drm_connector_funcs tegra_hdmi_connector_funcs = {
|
|
.dpms = drm_atomic_helper_connector_dpms,
|
|
.reset = drm_atomic_helper_connector_reset,
|
|
.detect = tegra_hdmi_connector_detect,
|
|
.fill_modes = drm_helper_probe_single_connector_modes,
|
|
.destroy = tegra_output_connector_destroy,
|
|
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
|
|
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
|
|
};
|
|
|
|
static enum drm_mode_status
|
|
tegra_hdmi_connector_mode_valid(struct drm_connector *connector,
|
|
struct drm_display_mode *mode)
|
|
{
|
|
struct tegra_output *output = connector_to_output(connector);
|
|
struct tegra_hdmi *hdmi = to_hdmi(output);
|
|
unsigned long pclk = mode->clock * 1000;
|
|
enum drm_mode_status status = MODE_OK;
|
|
struct clk *parent;
|
|
long err;
|
|
|
|
parent = clk_get_parent(hdmi->clk_parent);
|
|
|
|
err = clk_round_rate(parent, pclk * 4);
|
|
if (err <= 0)
|
|
status = MODE_NOCLOCK;
|
|
|
|
return status;
|
|
}
|
|
|
|
static const struct drm_connector_helper_funcs
|
|
tegra_hdmi_connector_helper_funcs = {
|
|
.get_modes = tegra_output_connector_get_modes,
|
|
.mode_valid = tegra_hdmi_connector_mode_valid,
|
|
};
|
|
|
|
static const struct drm_encoder_funcs tegra_hdmi_encoder_funcs = {
|
|
.destroy = tegra_output_encoder_destroy,
|
|
};
|
|
|
|
static void tegra_hdmi_encoder_disable(struct drm_encoder *encoder)
|
|
{
|
|
struct tegra_output *output = encoder_to_output(encoder);
|
|
struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
|
|
struct tegra_hdmi *hdmi = to_hdmi(output);
|
|
u32 value;
|
|
|
|
/*
|
|
* The following accesses registers of the display controller, so make
|
|
* sure it's only executed when the output is attached to one.
|
|
*/
|
|
if (dc) {
|
|
value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
|
|
value &= ~HDMI_ENABLE;
|
|
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
|
|
|
|
tegra_dc_commit(dc);
|
|
}
|
|
|
|
if (!hdmi->dvi) {
|
|
if (hdmi->stereo)
|
|
tegra_hdmi_disable_stereo_infoframe(hdmi);
|
|
|
|
tegra_hdmi_disable_audio_infoframe(hdmi);
|
|
tegra_hdmi_disable_avi_infoframe(hdmi);
|
|
tegra_hdmi_disable_audio(hdmi);
|
|
}
|
|
|
|
tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_ENABLE);
|
|
tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_MASK);
|
|
|
|
pm_runtime_put(hdmi->dev);
|
|
}
|
|
|
|
static void tegra_hdmi_encoder_enable(struct drm_encoder *encoder)
|
|
{
|
|
struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
|
|
unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
|
|
struct tegra_output *output = encoder_to_output(encoder);
|
|
struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
|
|
struct tegra_hdmi *hdmi = to_hdmi(output);
|
|
unsigned int pulse_start, div82;
|
|
int retries = 1000;
|
|
u32 value;
|
|
int err;
|
|
|
|
pm_runtime_get_sync(hdmi->dev);
|
|
|
|
/*
|
|
* Enable and unmask the HDA codec SCRATCH0 register interrupt. This
|
|
* is used for interoperability between the HDA codec driver and the
|
|
* HDMI driver.
|
|
*/
|
|
tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_ENABLE);
|
|
tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_MASK);
|
|
|
|
hdmi->pixel_clock = mode->clock * 1000;
|
|
h_sync_width = mode->hsync_end - mode->hsync_start;
|
|
h_back_porch = mode->htotal - mode->hsync_end;
|
|
h_front_porch = mode->hsync_start - mode->hdisplay;
|
|
|
|
err = clk_set_rate(hdmi->clk, hdmi->pixel_clock);
|
|
if (err < 0) {
|
|
dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n",
|
|
err);
|
|
}
|
|
|
|
DRM_DEBUG_KMS("HDMI clock rate: %lu Hz\n", clk_get_rate(hdmi->clk));
|
|
|
|
/* power up sequence */
|
|
value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
|
|
value &= ~SOR_PLL_PDBG;
|
|
tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
|
|
|
|
usleep_range(10, 20);
|
|
|
|
value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
|
|
value &= ~SOR_PLL_PWR;
|
|
tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
|
|
|
|
tegra_dc_writel(dc, VSYNC_H_POSITION(1),
|
|
DC_DISP_DISP_TIMING_OPTIONS);
|
|
tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888,
|
|
DC_DISP_DISP_COLOR_CONTROL);
|
|
|
|
/* video_preamble uses h_pulse2 */
|
|
pulse_start = 1 + h_sync_width + h_back_porch - 10;
|
|
|
|
tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
|
|
|
|
value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
|
|
PULSE_LAST_END_A;
|
|
tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
|
|
|
|
value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
|
|
tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
|
|
|
|
value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
|
|
VSYNC_WINDOW_ENABLE;
|
|
tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
|
|
|
|
if (dc->pipe)
|
|
value = HDMI_SRC_DISPLAYB;
|
|
else
|
|
value = HDMI_SRC_DISPLAYA;
|
|
|
|
if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
|
|
(mode->vdisplay == 576)))
|
|
tegra_hdmi_writel(hdmi,
|
|
value | ARM_VIDEO_RANGE_FULL,
|
|
HDMI_NV_PDISP_INPUT_CONTROL);
|
|
else
|
|
tegra_hdmi_writel(hdmi,
|
|
value | ARM_VIDEO_RANGE_LIMITED,
|
|
HDMI_NV_PDISP_INPUT_CONTROL);
|
|
|
|
div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
|
|
value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
|
|
tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
|
|
|
|
hdmi->dvi = !tegra_output_is_hdmi(output);
|
|
if (!hdmi->dvi) {
|
|
err = tegra_hdmi_setup_audio(hdmi);
|
|
if (err < 0)
|
|
hdmi->dvi = true;
|
|
}
|
|
|
|
if (hdmi->config->has_hda)
|
|
tegra_hdmi_write_eld(hdmi);
|
|
|
|
rekey = HDMI_REKEY_DEFAULT;
|
|
value = HDMI_CTRL_REKEY(rekey);
|
|
value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
|
|
h_front_porch - rekey - 18) / 32);
|
|
|
|
if (!hdmi->dvi)
|
|
value |= HDMI_CTRL_ENABLE;
|
|
|
|
tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
|
|
|
|
if (!hdmi->dvi) {
|
|
tegra_hdmi_setup_avi_infoframe(hdmi, mode);
|
|
tegra_hdmi_setup_audio_infoframe(hdmi);
|
|
|
|
if (hdmi->stereo)
|
|
tegra_hdmi_setup_stereo_infoframe(hdmi);
|
|
}
|
|
|
|
/* TMDS CONFIG */
|
|
for (i = 0; i < hdmi->config->num_tmds; i++) {
|
|
if (hdmi->pixel_clock <= hdmi->config->tmds[i].pclk) {
|
|
tegra_hdmi_setup_tmds(hdmi, &hdmi->config->tmds[i]);
|
|
break;
|
|
}
|
|
}
|
|
|
|
tegra_hdmi_writel(hdmi,
|
|
SOR_SEQ_PU_PC(0) |
|
|
SOR_SEQ_PU_PC_ALT(0) |
|
|
SOR_SEQ_PD_PC(8) |
|
|
SOR_SEQ_PD_PC_ALT(8),
|
|
HDMI_NV_PDISP_SOR_SEQ_CTL);
|
|
|
|
value = SOR_SEQ_INST_WAIT_TIME(1) |
|
|
SOR_SEQ_INST_WAIT_UNITS_VSYNC |
|
|
SOR_SEQ_INST_HALT |
|
|
SOR_SEQ_INST_PIN_A_LOW |
|
|
SOR_SEQ_INST_PIN_B_LOW |
|
|
SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
|
|
|
|
tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
|
|
tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
|
|
|
|
value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM);
|
|
value &= ~SOR_CSTM_ROTCLK(~0);
|
|
value |= SOR_CSTM_ROTCLK(2);
|
|
value |= SOR_CSTM_PLLDIV;
|
|
value &= ~SOR_CSTM_LVDS_ENABLE;
|
|
value &= ~SOR_CSTM_MODE_MASK;
|
|
value |= SOR_CSTM_MODE_TMDS;
|
|
tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
|
|
|
|
/* start SOR */
|
|
tegra_hdmi_writel(hdmi,
|
|
SOR_PWR_NORMAL_STATE_PU |
|
|
SOR_PWR_NORMAL_START_NORMAL |
|
|
SOR_PWR_SAFE_STATE_PD |
|
|
SOR_PWR_SETTING_NEW_TRIGGER,
|
|
HDMI_NV_PDISP_SOR_PWR);
|
|
tegra_hdmi_writel(hdmi,
|
|
SOR_PWR_NORMAL_STATE_PU |
|
|
SOR_PWR_NORMAL_START_NORMAL |
|
|
SOR_PWR_SAFE_STATE_PD |
|
|
SOR_PWR_SETTING_NEW_DONE,
|
|
HDMI_NV_PDISP_SOR_PWR);
|
|
|
|
do {
|
|
BUG_ON(--retries < 0);
|
|
value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
|
|
} while (value & SOR_PWR_SETTING_NEW_PENDING);
|
|
|
|
value = SOR_STATE_ASY_CRCMODE_COMPLETE |
|
|
SOR_STATE_ASY_OWNER_HEAD0 |
|
|
SOR_STATE_ASY_SUBOWNER_BOTH |
|
|
SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
|
|
SOR_STATE_ASY_DEPOL_POS;
|
|
|
|
/* setup sync polarities */
|
|
if (mode->flags & DRM_MODE_FLAG_PHSYNC)
|
|
value |= SOR_STATE_ASY_HSYNCPOL_POS;
|
|
|
|
if (mode->flags & DRM_MODE_FLAG_NHSYNC)
|
|
value |= SOR_STATE_ASY_HSYNCPOL_NEG;
|
|
|
|
if (mode->flags & DRM_MODE_FLAG_PVSYNC)
|
|
value |= SOR_STATE_ASY_VSYNCPOL_POS;
|
|
|
|
if (mode->flags & DRM_MODE_FLAG_NVSYNC)
|
|
value |= SOR_STATE_ASY_VSYNCPOL_NEG;
|
|
|
|
tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
|
|
|
|
value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
|
|
tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
|
|
|
|
tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
|
|
tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
|
|
tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
|
|
HDMI_NV_PDISP_SOR_STATE1);
|
|
tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
|
|
|
|
value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
|
|
value |= HDMI_ENABLE;
|
|
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
|
|
|
|
tegra_dc_commit(dc);
|
|
|
|
if (!hdmi->dvi) {
|
|
tegra_hdmi_enable_avi_infoframe(hdmi);
|
|
tegra_hdmi_enable_audio_infoframe(hdmi);
|
|
tegra_hdmi_enable_audio(hdmi);
|
|
|
|
if (hdmi->stereo)
|
|
tegra_hdmi_enable_stereo_infoframe(hdmi);
|
|
}
|
|
|
|
/* TODO: add HDCP support */
|
|
}
|
|
|
|
static int
|
|
tegra_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
|
|
struct drm_crtc_state *crtc_state,
|
|
struct drm_connector_state *conn_state)
|
|
{
|
|
struct tegra_output *output = encoder_to_output(encoder);
|
|
struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
|
|
unsigned long pclk = crtc_state->mode.clock * 1000;
|
|
struct tegra_hdmi *hdmi = to_hdmi(output);
|
|
int err;
|
|
|
|
err = tegra_dc_state_setup_clock(dc, crtc_state, hdmi->clk_parent,
|
|
pclk, 0);
|
|
if (err < 0) {
|
|
dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
static const struct drm_encoder_helper_funcs tegra_hdmi_encoder_helper_funcs = {
|
|
.disable = tegra_hdmi_encoder_disable,
|
|
.enable = tegra_hdmi_encoder_enable,
|
|
.atomic_check = tegra_hdmi_encoder_atomic_check,
|
|
};
|
|
|
|
static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
|
|
{
|
|
struct drm_info_node *node = s->private;
|
|
struct tegra_hdmi *hdmi = node->info_ent->data;
|
|
struct drm_crtc *crtc = hdmi->output.encoder.crtc;
|
|
struct drm_device *drm = node->minor->dev;
|
|
int err = 0;
|
|
|
|
drm_modeset_lock_all(drm);
|
|
|
|
if (!crtc || !crtc->state->active) {
|
|
err = -EBUSY;
|
|
goto unlock;
|
|
}
|
|
|
|
#define DUMP_REG(name) \
|
|
seq_printf(s, "%-56s %#05x %08x\n", #name, name, \
|
|
tegra_hdmi_readl(hdmi, name))
|
|
|
|
DUMP_REG(HDMI_CTXSW);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
|
|
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
|
|
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
|
|
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
|
|
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
|
|
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
|
|
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
|
|
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
|
|
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
|
|
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
|
|
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
|
|
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
|
|
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
|
|
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
|
|
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
|
|
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
|
|
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
|
|
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
|
|
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
|
|
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
|
|
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
|
|
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
|
|
DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
|
|
DUMP_REG(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(0));
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(1));
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(2));
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(3));
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(4));
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(5));
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(6));
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(7));
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(8));
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(9));
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(10));
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(11));
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(12));
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(13));
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(14));
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(15));
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
|
|
DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
|
|
DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
|
|
DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
|
|
DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
|
|
DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
|
|
DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
|
|
DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
|
|
DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
|
|
DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
|
|
DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
|
|
DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
|
|
DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
|
|
DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
|
|
DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
|
|
DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
|
|
DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
|
|
DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
|
|
DUMP_REG(HDMI_NV_PDISP_SCRATCH);
|
|
DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
|
|
DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
|
|
DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
|
|
DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
|
|
DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
|
|
DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
|
|
DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
|
|
DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
|
|
DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
|
|
DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
|
|
DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
|
|
DUMP_REG(HDMI_NV_PDISP_INT_STATUS);
|
|
DUMP_REG(HDMI_NV_PDISP_INT_MASK);
|
|
DUMP_REG(HDMI_NV_PDISP_INT_ENABLE);
|
|
DUMP_REG(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
|
|
|
|
#undef DUMP_REG
|
|
|
|
unlock:
|
|
drm_modeset_unlock_all(drm);
|
|
return err;
|
|
}
|
|
|
|
static struct drm_info_list debugfs_files[] = {
|
|
{ "regs", tegra_hdmi_show_regs, 0, NULL },
|
|
};
|
|
|
|
static int tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi,
|
|
struct drm_minor *minor)
|
|
{
|
|
unsigned int i;
|
|
int err;
|
|
|
|
hdmi->debugfs = debugfs_create_dir("hdmi", minor->debugfs_root);
|
|
if (!hdmi->debugfs)
|
|
return -ENOMEM;
|
|
|
|
hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
|
|
GFP_KERNEL);
|
|
if (!hdmi->debugfs_files) {
|
|
err = -ENOMEM;
|
|
goto remove;
|
|
}
|
|
|
|
for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
|
|
hdmi->debugfs_files[i].data = hdmi;
|
|
|
|
err = drm_debugfs_create_files(hdmi->debugfs_files,
|
|
ARRAY_SIZE(debugfs_files),
|
|
hdmi->debugfs, minor);
|
|
if (err < 0)
|
|
goto free;
|
|
|
|
hdmi->minor = minor;
|
|
|
|
return 0;
|
|
|
|
free:
|
|
kfree(hdmi->debugfs_files);
|
|
hdmi->debugfs_files = NULL;
|
|
remove:
|
|
debugfs_remove(hdmi->debugfs);
|
|
hdmi->debugfs = NULL;
|
|
|
|
return err;
|
|
}
|
|
|
|
static void tegra_hdmi_debugfs_exit(struct tegra_hdmi *hdmi)
|
|
{
|
|
drm_debugfs_remove_files(hdmi->debugfs_files, ARRAY_SIZE(debugfs_files),
|
|
hdmi->minor);
|
|
hdmi->minor = NULL;
|
|
|
|
kfree(hdmi->debugfs_files);
|
|
hdmi->debugfs_files = NULL;
|
|
|
|
debugfs_remove(hdmi->debugfs);
|
|
hdmi->debugfs = NULL;
|
|
}
|
|
|
|
static int tegra_hdmi_init(struct host1x_client *client)
|
|
{
|
|
struct drm_device *drm = dev_get_drvdata(client->parent);
|
|
struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
|
|
int err;
|
|
|
|
hdmi->output.dev = client->dev;
|
|
|
|
drm_connector_init(drm, &hdmi->output.connector,
|
|
&tegra_hdmi_connector_funcs,
|
|
DRM_MODE_CONNECTOR_HDMIA);
|
|
drm_connector_helper_add(&hdmi->output.connector,
|
|
&tegra_hdmi_connector_helper_funcs);
|
|
hdmi->output.connector.dpms = DRM_MODE_DPMS_OFF;
|
|
|
|
drm_encoder_init(drm, &hdmi->output.encoder, &tegra_hdmi_encoder_funcs,
|
|
DRM_MODE_ENCODER_TMDS, NULL);
|
|
drm_encoder_helper_add(&hdmi->output.encoder,
|
|
&tegra_hdmi_encoder_helper_funcs);
|
|
|
|
drm_mode_connector_attach_encoder(&hdmi->output.connector,
|
|
&hdmi->output.encoder);
|
|
drm_connector_register(&hdmi->output.connector);
|
|
|
|
err = tegra_output_init(drm, &hdmi->output);
|
|
if (err < 0) {
|
|
dev_err(client->dev, "failed to initialize output: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
hdmi->output.encoder.possible_crtcs = 0x3;
|
|
|
|
if (IS_ENABLED(CONFIG_DEBUG_FS)) {
|
|
err = tegra_hdmi_debugfs_init(hdmi, drm->primary);
|
|
if (err < 0)
|
|
dev_err(client->dev, "debugfs setup failed: %d\n", err);
|
|
}
|
|
|
|
err = regulator_enable(hdmi->hdmi);
|
|
if (err < 0) {
|
|
dev_err(client->dev, "failed to enable HDMI regulator: %d\n",
|
|
err);
|
|
return err;
|
|
}
|
|
|
|
err = regulator_enable(hdmi->pll);
|
|
if (err < 0) {
|
|
dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
err = regulator_enable(hdmi->vdd);
|
|
if (err < 0) {
|
|
dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_hdmi_exit(struct host1x_client *client)
|
|
{
|
|
struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
|
|
|
|
tegra_output_exit(&hdmi->output);
|
|
|
|
regulator_disable(hdmi->vdd);
|
|
regulator_disable(hdmi->pll);
|
|
regulator_disable(hdmi->hdmi);
|
|
|
|
if (IS_ENABLED(CONFIG_DEBUG_FS))
|
|
tegra_hdmi_debugfs_exit(hdmi);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct host1x_client_ops hdmi_client_ops = {
|
|
.init = tegra_hdmi_init,
|
|
.exit = tegra_hdmi_exit,
|
|
};
|
|
|
|
static const struct tegra_hdmi_config tegra20_hdmi_config = {
|
|
.tmds = tegra20_tmds_config,
|
|
.num_tmds = ARRAY_SIZE(tegra20_tmds_config),
|
|
.fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
|
|
.fuse_override_value = 1 << 31,
|
|
.has_sor_io_peak_current = false,
|
|
.has_hda = false,
|
|
.has_hbr = false,
|
|
};
|
|
|
|
static const struct tegra_hdmi_config tegra30_hdmi_config = {
|
|
.tmds = tegra30_tmds_config,
|
|
.num_tmds = ARRAY_SIZE(tegra30_tmds_config),
|
|
.fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
|
|
.fuse_override_value = 1 << 31,
|
|
.has_sor_io_peak_current = false,
|
|
.has_hda = true,
|
|
.has_hbr = false,
|
|
};
|
|
|
|
static const struct tegra_hdmi_config tegra114_hdmi_config = {
|
|
.tmds = tegra114_tmds_config,
|
|
.num_tmds = ARRAY_SIZE(tegra114_tmds_config),
|
|
.fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
|
|
.fuse_override_value = 1 << 31,
|
|
.has_sor_io_peak_current = true,
|
|
.has_hda = true,
|
|
.has_hbr = true,
|
|
};
|
|
|
|
static const struct tegra_hdmi_config tegra124_hdmi_config = {
|
|
.tmds = tegra124_tmds_config,
|
|
.num_tmds = ARRAY_SIZE(tegra124_tmds_config),
|
|
.fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
|
|
.fuse_override_value = 1 << 31,
|
|
.has_sor_io_peak_current = true,
|
|
.has_hda = true,
|
|
.has_hbr = true,
|
|
};
|
|
|
|
static const struct of_device_id tegra_hdmi_of_match[] = {
|
|
{ .compatible = "nvidia,tegra124-hdmi", .data = &tegra124_hdmi_config },
|
|
{ .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config },
|
|
{ .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config },
|
|
{ .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, tegra_hdmi_of_match);
|
|
|
|
static void hda_format_parse(unsigned int format, unsigned int *rate,
|
|
unsigned int *channels)
|
|
{
|
|
unsigned int mul, div;
|
|
|
|
if (format & AC_FMT_BASE_44K)
|
|
*rate = 44100;
|
|
else
|
|
*rate = 48000;
|
|
|
|
mul = (format & AC_FMT_MULT_MASK) >> AC_FMT_MULT_SHIFT;
|
|
div = (format & AC_FMT_DIV_MASK) >> AC_FMT_DIV_SHIFT;
|
|
|
|
*rate = *rate * (mul + 1) / (div + 1);
|
|
|
|
*channels = (format & AC_FMT_CHAN_MASK) >> AC_FMT_CHAN_SHIFT;
|
|
}
|
|
|
|
static irqreturn_t tegra_hdmi_irq(int irq, void *data)
|
|
{
|
|
struct tegra_hdmi *hdmi = data;
|
|
u32 value;
|
|
int err;
|
|
|
|
value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_INT_STATUS);
|
|
tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_INT_STATUS);
|
|
|
|
if (value & INT_CODEC_SCRATCH0) {
|
|
unsigned int format;
|
|
u32 value;
|
|
|
|
value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0);
|
|
|
|
if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
|
|
unsigned int sample_rate, channels;
|
|
|
|
format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
|
|
|
|
hda_format_parse(format, &sample_rate, &channels);
|
|
|
|
hdmi->audio_sample_rate = sample_rate;
|
|
hdmi->audio_channels = channels;
|
|
|
|
err = tegra_hdmi_setup_audio(hdmi);
|
|
if (err < 0) {
|
|
tegra_hdmi_disable_audio_infoframe(hdmi);
|
|
tegra_hdmi_disable_audio(hdmi);
|
|
} else {
|
|
tegra_hdmi_setup_audio_infoframe(hdmi);
|
|
tegra_hdmi_enable_audio_infoframe(hdmi);
|
|
tegra_hdmi_enable_audio(hdmi);
|
|
}
|
|
} else {
|
|
tegra_hdmi_disable_audio_infoframe(hdmi);
|
|
tegra_hdmi_disable_audio(hdmi);
|
|
}
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int tegra_hdmi_probe(struct platform_device *pdev)
|
|
{
|
|
const struct of_device_id *match;
|
|
struct tegra_hdmi *hdmi;
|
|
struct resource *regs;
|
|
int err;
|
|
|
|
match = of_match_node(tegra_hdmi_of_match, pdev->dev.of_node);
|
|
if (!match)
|
|
return -ENODEV;
|
|
|
|
hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
|
|
if (!hdmi)
|
|
return -ENOMEM;
|
|
|
|
hdmi->config = match->data;
|
|
hdmi->dev = &pdev->dev;
|
|
|
|
hdmi->audio_source = AUTO;
|
|
hdmi->audio_sample_rate = 48000;
|
|
hdmi->audio_channels = 2;
|
|
hdmi->stereo = false;
|
|
hdmi->dvi = false;
|
|
|
|
hdmi->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(hdmi->clk)) {
|
|
dev_err(&pdev->dev, "failed to get clock\n");
|
|
return PTR_ERR(hdmi->clk);
|
|
}
|
|
|
|
hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi");
|
|
if (IS_ERR(hdmi->rst)) {
|
|
dev_err(&pdev->dev, "failed to get reset\n");
|
|
return PTR_ERR(hdmi->rst);
|
|
}
|
|
|
|
hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
|
|
if (IS_ERR(hdmi->clk_parent))
|
|
return PTR_ERR(hdmi->clk_parent);
|
|
|
|
err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
|
|
if (err < 0) {
|
|
dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
hdmi->hdmi = devm_regulator_get(&pdev->dev, "hdmi");
|
|
if (IS_ERR(hdmi->hdmi)) {
|
|
dev_err(&pdev->dev, "failed to get HDMI regulator\n");
|
|
return PTR_ERR(hdmi->hdmi);
|
|
}
|
|
|
|
hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
|
|
if (IS_ERR(hdmi->pll)) {
|
|
dev_err(&pdev->dev, "failed to get PLL regulator\n");
|
|
return PTR_ERR(hdmi->pll);
|
|
}
|
|
|
|
hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
|
|
if (IS_ERR(hdmi->vdd)) {
|
|
dev_err(&pdev->dev, "failed to get VDD regulator\n");
|
|
return PTR_ERR(hdmi->vdd);
|
|
}
|
|
|
|
hdmi->output.dev = &pdev->dev;
|
|
|
|
err = tegra_output_probe(&hdmi->output);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
hdmi->regs = devm_ioremap_resource(&pdev->dev, regs);
|
|
if (IS_ERR(hdmi->regs))
|
|
return PTR_ERR(hdmi->regs);
|
|
|
|
err = platform_get_irq(pdev, 0);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
hdmi->irq = err;
|
|
|
|
err = devm_request_irq(hdmi->dev, hdmi->irq, tegra_hdmi_irq, 0,
|
|
dev_name(hdmi->dev), hdmi);
|
|
if (err < 0) {
|
|
dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n",
|
|
hdmi->irq, err);
|
|
return err;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, hdmi);
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
INIT_LIST_HEAD(&hdmi->client.list);
|
|
hdmi->client.ops = &hdmi_client_ops;
|
|
hdmi->client.dev = &pdev->dev;
|
|
|
|
err = host1x_client_register(&hdmi->client);
|
|
if (err < 0) {
|
|
dev_err(&pdev->dev, "failed to register host1x client: %d\n",
|
|
err);
|
|
return err;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_hdmi_remove(struct platform_device *pdev)
|
|
{
|
|
struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
|
|
int err;
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
err = host1x_client_unregister(&hdmi->client);
|
|
if (err < 0) {
|
|
dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
|
|
err);
|
|
return err;
|
|
}
|
|
|
|
tegra_output_remove(&hdmi->output);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int tegra_hdmi_suspend(struct device *dev)
|
|
{
|
|
struct tegra_hdmi *hdmi = dev_get_drvdata(dev);
|
|
int err;
|
|
|
|
err = reset_control_assert(hdmi->rst);
|
|
if (err < 0) {
|
|
dev_err(dev, "failed to assert reset: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
usleep_range(1000, 2000);
|
|
|
|
clk_disable_unprepare(hdmi->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_hdmi_resume(struct device *dev)
|
|
{
|
|
struct tegra_hdmi *hdmi = dev_get_drvdata(dev);
|
|
int err;
|
|
|
|
err = clk_prepare_enable(hdmi->clk);
|
|
if (err < 0) {
|
|
dev_err(dev, "failed to enable clock: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
usleep_range(1000, 2000);
|
|
|
|
err = reset_control_deassert(hdmi->rst);
|
|
if (err < 0) {
|
|
dev_err(dev, "failed to deassert reset: %d\n", err);
|
|
clk_disable_unprepare(hdmi->clk);
|
|
return err;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static const struct dev_pm_ops tegra_hdmi_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(tegra_hdmi_suspend, tegra_hdmi_resume, NULL)
|
|
};
|
|
|
|
struct platform_driver tegra_hdmi_driver = {
|
|
.driver = {
|
|
.name = "tegra-hdmi",
|
|
.of_match_table = tegra_hdmi_of_match,
|
|
.pm = &tegra_hdmi_pm_ops,
|
|
},
|
|
.probe = tegra_hdmi_probe,
|
|
.remove = tegra_hdmi_remove,
|
|
};
|